147 lines
3.7 KiB
ArmAsm
147 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/02 Bernard The first version
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* 2018/12/27 Jesven Add SMP schedule
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*/
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#include "cpuport.h"
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.section .text.entry
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.align 2
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.global trap_entry
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trap_entry:
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#ifdef ARCH_RISCV_FPU
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addi sp, sp, -32 * FREGBYTES
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FSTORE f0, 0 * FREGBYTES(sp)
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FSTORE f1, 1 * FREGBYTES(sp)
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FSTORE f2, 2 * FREGBYTES(sp)
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FSTORE f3, 3 * FREGBYTES(sp)
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FSTORE f4, 4 * FREGBYTES(sp)
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FSTORE f5, 5 * FREGBYTES(sp)
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FSTORE f6, 6 * FREGBYTES(sp)
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FSTORE f7, 7 * FREGBYTES(sp)
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FSTORE f8, 8 * FREGBYTES(sp)
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FSTORE f9, 9 * FREGBYTES(sp)
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FSTORE f10, 10 * FREGBYTES(sp)
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FSTORE f11, 11 * FREGBYTES(sp)
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FSTORE f12, 12 * FREGBYTES(sp)
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FSTORE f13, 13 * FREGBYTES(sp)
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FSTORE f14, 14 * FREGBYTES(sp)
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FSTORE f15, 15 * FREGBYTES(sp)
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FSTORE f16, 16 * FREGBYTES(sp)
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FSTORE f17, 17 * FREGBYTES(sp)
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FSTORE f18, 18 * FREGBYTES(sp)
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FSTORE f19, 19 * FREGBYTES(sp)
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FSTORE f20, 20 * FREGBYTES(sp)
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FSTORE f21, 21 * FREGBYTES(sp)
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FSTORE f22, 22 * FREGBYTES(sp)
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FSTORE f23, 23 * FREGBYTES(sp)
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FSTORE f24, 24 * FREGBYTES(sp)
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FSTORE f25, 25 * FREGBYTES(sp)
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FSTORE f26, 26 * FREGBYTES(sp)
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FSTORE f27, 27 * FREGBYTES(sp)
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FSTORE f28, 28 * FREGBYTES(sp)
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FSTORE f29, 29 * FREGBYTES(sp)
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FSTORE f30, 30 * FREGBYTES(sp)
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FSTORE f31, 31 * FREGBYTES(sp)
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#endif
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/* save thread context to thread stack */
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addi sp, sp, -32 * REGBYTES
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STORE x1, 1 * REGBYTES(sp)
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csrr x1, mstatus
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STORE x1, 2 * REGBYTES(sp)
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csrr x1, mepc
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STORE x1, 0 * REGBYTES(sp)
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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/* switch to interrupt stack */
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move s0, sp
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/* get cpu id */
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csrr t0, mhartid
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/* switch interrupt stack of current cpu */
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la sp, __stack_start__
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addi t1, t0, 1
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li t2, __STACKSIZE__
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mul t1, t1, t2
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add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
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/* handle interrupt */
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call rt_interrupt_enter
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csrr a0, mcause
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csrr a1, mepc
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mv a2, s0
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call handle_trap
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call rt_interrupt_leave
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#ifdef RT_USING_SMP
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/* s0 --> sp */
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mv sp, s0
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mv a0, s0
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call rt_scheduler_do_irq_switch
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tail rt_hw_context_switch_exit
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#else
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/* switch to from_thread stack */
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move sp, s0
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/* need to switch new thread */
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la s0, rt_thread_switch_interrupt_flag
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lw s2, 0(s0)
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beqz s2, spurious_interrupt
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sw zero, 0(s0)
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la s0, rt_interrupt_from_thread
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LOAD s1, 0(s0)
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STORE sp, 0(s1)
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la s0, rt_interrupt_to_thread
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LOAD s1, 0(s0)
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LOAD sp, 0(s1)
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#endif
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spurious_interrupt:
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tail rt_hw_context_switch_exit
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