141 lines
3.4 KiB
C
141 lines
3.4 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-06 Bernard first version
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* 2014-04-03 Grissiom port to VMM
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "realview.h"
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#include "gic.h"
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#ifdef RT_USING_VMM
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#include <vmm.h>
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#endif
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#define MAX_HANDLERS NR_IRQS_PBA8
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extern volatile rt_uint8_t rt_interrupt_nest;
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/* exception and interrupt handler table */
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struct rt_irq_desc isr_table[MAX_HANDLERS];
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/* Those varibles will be accessed in ISR, so we need to share them. */
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rt_uint32_t rt_interrupt_from_thread SECTION(".bss.share.int");
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rt_uint32_t rt_interrupt_to_thread SECTION(".bss.share.int");
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rt_uint32_t rt_thread_switch_interrupt_flag SECTION(".bss.share.int");
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const unsigned int VECTOR_BASE = 0x00;
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extern void rt_cpu_vector_set_base(unsigned int addr);
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extern int system_vectors;
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static void rt_hw_vector_init(void)
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{
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#ifndef RT_USING_VMM
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unsigned int *dest = (unsigned int *)VECTOR_BASE;
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unsigned int *src = (unsigned int *)&system_vectors;
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rt_memcpy(dest, src, 16 * 4);
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rt_cpu_vector_set_base(VECTOR_BASE);
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#endif
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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rt_uint32_t gic_cpu_base;
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rt_uint32_t gic_dist_base;
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/* initialize vector table */
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rt_hw_vector_init();
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/* initialize exceptions table */
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rt_memset(isr_table, 0x00, sizeof(isr_table));
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/* initialize ARM GIC */
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#ifdef RT_USING_VMM
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gic_dist_base = vmm_find_iomap("GIC_DIST");
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gic_cpu_base = vmm_find_iomap("GIC_CPU");
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#else
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gic_dist_base = REALVIEW_GIC_DIST_BASE;
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gic_cpu_base = REALVIEW_GIC_CPU_BASE;
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#endif
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arm_gic_dist_init(0, gic_dist_base, 0);
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arm_gic_cpu_init(0, gic_cpu_base);
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/*arm_gic_dump_type(0);*/
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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arm_gic_mask(0, vector);
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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arm_gic_umask(0, vector);
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector < MAX_HANDLERS)
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{
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old_handler = isr_table[vector].handler;
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if (handler != RT_NULL)
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{
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#ifdef RT_USING_INTERRUPT_INFO
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rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
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#endif /* RT_USING_INTERRUPT_INFO */
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isr_table[vector].handler = handler;
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isr_table[vector].param = param;
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}
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}
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return old_handler;
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}
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/**
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* Trigger a software IRQ
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*
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* Since we are running in single core, the target CPU are always CPU0.
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*/
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void rt_hw_interrupt_trigger(int vector)
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{
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arm_gic_trigger(0, 1, vector);
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}
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void rt_hw_interrupt_clear(int vector)
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{
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arm_gic_clear_sgi(0, 1, vector);
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}
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