101 lines
2.6 KiB
C
101 lines
2.6 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-03-29 quanzhao the first version
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*/
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#include <rthw.h>
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#include <rtdef.h>
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rt_inline rt_uint32_t rt_cpu_icache_line_size(void)
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{
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rt_uint32_t ctr;
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asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr));
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return 4 << (ctr & 0xF);
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}
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rt_inline rt_uint32_t rt_cpu_dcache_line_size(void)
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{
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rt_uint32_t ctr;
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asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr));
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return 4 << ((ctr >> 16) & 0xF);
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}
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void rt_hw_cpu_icache_invalidate(void *addr, int size)
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{
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rt_uint32_t line_size = rt_cpu_icache_line_size();
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rt_uint32_t start_addr = (rt_uint32_t)addr;
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rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
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asm volatile ("dmb":::"memory");
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start_addr &= ~(line_size-1);
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end_addr &= ~(line_size-1);
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while (start_addr < end_addr)
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */
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start_addr += line_size;
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}
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asm volatile ("dsb\n\tisb":::"memory");
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}
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void rt_hw_cpu_dcache_invalidate(void *addr, int size)
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{
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rt_uint32_t line_size = rt_cpu_dcache_line_size();
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rt_uint32_t start_addr = (rt_uint32_t)addr;
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rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
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asm volatile ("dmb":::"memory");
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start_addr &= ~(line_size-1);
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end_addr &= ~(line_size-1);
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while (start_addr < end_addr)
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */
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start_addr += line_size;
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}
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asm volatile ("dsb":::"memory");
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}
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void rt_hw_cpu_dcache_clean(void *addr, int size)
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{
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rt_uint32_t line_size = rt_cpu_dcache_line_size();
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rt_uint32_t start_addr = (rt_uint32_t)addr;
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rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
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asm volatile ("dmb":::"memory");
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start_addr &= ~(line_size-1);
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end_addr &= ~(line_size-1);
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while (start_addr < end_addr)
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{
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asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */
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start_addr += line_size;
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}
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asm volatile ("dsb":::"memory");
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}
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void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_INVALIDATE)
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rt_hw_cpu_icache_invalidate(addr, size);
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}
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void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_FLUSH)
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rt_hw_cpu_dcache_clean(addr, size);
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else if (ops == RT_HW_CACHE_INVALIDATE)
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rt_hw_cpu_dcache_invalidate(addr, size);
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}
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rt_base_t rt_hw_cpu_icache_status(void)
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{
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return 0;
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}
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rt_base_t rt_hw_cpu_dcache_status(void)
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{
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return 0;
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}
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