190 lines
3.9 KiB
C
190 lines
3.9 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2012-01-10 bernard porting to AM1808
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*/
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#include <rtthread.h>
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#include "am33xx.h"
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#include <mmu.h>
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extern void rt_cpu_dcache_disable(void);
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extern void rt_hw_cpu_dcache_enable(void);
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extern void rt_cpu_icache_disable(void);
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extern void rt_hw_cpu_icache_enable(void);
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extern void rt_cpu_mmu_disable(void);
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extern void rt_cpu_mmu_enable(void);
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extern void rt_cpu_tlb_set(register rt_uint32_t i);
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void mmu_disable_dcache()
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{
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rt_cpu_dcache_disable();
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}
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void mmu_enable_dcache()
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{
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rt_hw_cpu_dcache_enable();
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}
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void mmu_disable_icache()
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{
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rt_cpu_icache_disable();
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}
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void mmu_enable_icache()
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{
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rt_hw_cpu_icache_enable();
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}
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void mmu_disable()
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{
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rt_cpu_mmu_disable();
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}
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void mmu_enable()
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{
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rt_cpu_mmu_enable();
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}
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void mmu_setttbase(register rt_uint32_t i)
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{
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register rt_uint32_t value;
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
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value = 0x55555555;
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asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
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rt_cpu_tlb_set(i);
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}
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void mmu_set_domain(register rt_uint32_t i)
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{
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asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 1);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 1);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while (ptr < buffer + size)
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{
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asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
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ptr += 32;
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}
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}
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~0x1f;
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while (ptr < buffer + size)
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
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ptr += 32;
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}
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}
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void mmu_invalidate_tlb()
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{
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asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
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}
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void mmu_invalidate_icache()
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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/* level1 page table */
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static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
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void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
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{
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volatile rt_uint32_t *pTT;
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volatile int i,nSec;
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pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
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nSec=(vaddrEnd>>20)-(vaddrStart>>20);
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for(i=0;i<=nSec;i++)
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{
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*pTT = attr |(((paddrStart>>20)+i)<<20);
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pTT++;
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}
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}
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/* set page table */
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RT_WEAK void mmu_setmtts(void)
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{
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mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */
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mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB); /* 126M cached DDR memory */
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mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB); /* 2M none-cached DDR memory */
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mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */
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}
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void rt_hw_mmu_init(void)
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{
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/* disable I/D cache */
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mmu_disable_dcache();
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mmu_disable_icache();
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mmu_disable();
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mmu_invalidate_tlb();
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mmu_setmtts();
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/* set MMU table address */
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mmu_setttbase((rt_uint32_t)_page_table);
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/* enables MMU */
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mmu_enable();
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/* enable Instruction Cache */
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mmu_enable_icache();
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/* enable Data Cache */
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mmu_enable_dcache();
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}
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