343 lines
9.2 KiB
C
343 lines
9.2 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2006-09-06 XuXinming first version
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* 2006-09-16 Bernard modify according to code style
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*/
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#ifndef __S3C44B0_H__
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#define __S3C44B0_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @addtogroup S3C44B0
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*/
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/*@{*/
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/*------------------------------------------------------------------------
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* ASIC Address Definition
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*----------------------------------------------------------------------*/
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#define S3C_REG *(volatile unsigned int *)
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#define S3C_REGW *(volatile unsigned short *)
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#define S3C_REGB *(volatile unsigned char *)
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/* System */
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#define SYSCFG (S3C_REG(0x1c00000))
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/* Cache */
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#define NCACHBE0 (S3C_REG(0x1c00004))
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#define NCACHBE1 (S3C_REG(0x1c00008))
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/* Bus control */
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#define SBUSCON (S3C_REG(0x1c40000))
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/* Memory control */
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#define BWSCON (S3C_REG(0x1c80000))
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#define BANKCON0 (S3C_REG(0x1c80004))
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#define BANKCON1 (S3C_REG(0x1c80008))
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#define BANKCON2 (S3C_REG(0x1c8000c))
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#define BANKCON3 (S3C_REG(0x1c80010))
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#define BANKCON4 (S3C_REG(0x1c80014))
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#define BANKCON5 (S3C_REG(0x1c80018))
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#define BANKCON6 (S3C_REG(0x1c8001c))
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#define BANKCON7 (S3C_REG(0x1c80020))
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#define REFRESH (S3C_REG(0x1c80024))
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#define BANKSIZE (S3C_REG(0x1c80028))
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#define MRSRB6 (S3C_REG(0x1c8002c))
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#define MRSRB7 (S3C_REG(0x1c80030))
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/* UART */
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#define ULCON0 (S3C_REG(0x1d00000))
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#define ULCON1 (S3C_REG(0x1d04000))
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#define UCON0 (S3C_REG(0x1d00004))
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#define UCON1 (S3C_REG(0x1d04004))
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#define UFCON0 (S3C_REG(0x1d00008))
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#define UFCON1 (S3C_REG(0x1d04008))
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#define UMCON0 (S3C_REG(0x1d0000c))
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#define UMCON1 (S3C_REG(0x1d0400c))
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#define UTRSTAT0 (S3C_REG(0x1d00010))
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#define UTRSTAT1 (S3C_REG(0x1d04010))
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#define UERSTAT0 (S3C_REG(0x1d00014))
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#define UERSTAT1 (S3C_REG(0x1d04014))
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#define UFSTAT0 (S3C_REG(0x1d00018))
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#define UFSTAT1 (S3C_REG(0x1d04018))
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#define UMSTAT0 (S3C_REG(0x1d0001c))
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#define UMSTAT1 (S3C_REG(0x1d0401c))
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#define UBRDIV0 (S3C_REG(0x1d00028))
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#define UBRDIV1 (S3C_REG(0x1d04028))
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#define UTXH0 (S3C_REGB(0x1d00020))
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#define UTXH1 (S3C_REGB(0x1d04020))
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#define URXH0 (S3C_REGB(0x1d00024))
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#define URXH1 (S3C_REGB(0x1d04024))
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/* SIO */
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#define SIOCON (S3C_REG(0x1d14000))
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#define SIODAT (S3C_REG(0x1d14004))
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#define SBRDR (S3C_REG(0x1d14008))
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#define IVTCNT (S3C_REG(0x1d1400c))
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#define DCNTZ (S3C_REG(0x1d14010))
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/* IIS */
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#define IISCON (S3C_REG(0x1d18000))
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#define IISMOD (S3C_REG(0x1d18004))
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#define IISPSR (S3C_REG(0x1d18008))
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#define IISFCON (S3C_REG(0x1d1800c))
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#define IISFIF (S3C_REQW(0x1d18010))
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/* I/O Port */
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#define PCONA (S3C_REG(0x1d20000))
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#define PDATA (S3C_REG(0x1d20004))
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#define PCONB (S3C_REG(0x1d20008))
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#define PDATB (S3C_REG(0x1d2000c))
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#define PCONC (S3C_REG(0x1d20010))
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#define PDATC (S3C_REG(0x1d20014))
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#define PUPC (S3C_REG(0x1d20018))
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#define PCOND (S3C_REG(0x1d2001c))
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#define PDATD (S3C_REG(0x1d20020))
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#define PUPD (S3C_REG(0x1d20024))
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#define PCONE (S3C_REG(0x1d20028))
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#define PDATE (S3C_REG(0x1d2002c))
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#define PUPE (S3C_REG(0x1d20030))
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#define PCONF (S3C_REG(0x1d20034))
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#define PDATF (S3C_REG(0x1d20038))
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#define PUPF (S3C_REG(0x1d2003c))
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#define PCONG (S3C_REG(0x1d20040))
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#define PDATG (S3C_REG(0x1d20044))
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#define PUPG (S3C_REG(0x1d20048))
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#define SPUCR (S3C_REG(0x1d2004c))
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#define EXTINT (S3C_REG(0x1d20050))
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#define EXTINTPND (S3C_REG(0x1d20054))
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/* Watchdog */
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#define WTCON (S3C_REG(0x1d30000))
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#define WTDAT (S3C_REG(0x1d30004))
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#define WTCNT (S3C_REG(0x1d30008))
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/* ADC */
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#define ADCCON (S3C_REG(0x1d40000))
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#define ADCPSR (S3C_REG(0x1d40004))
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#define ADCDAT (S3C_REG(0x1d40008))
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/* Timer */
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#define TCFG0 (S3C_REG(0x1d50000))
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#define TCFG1 (S3C_REG(0x1d50004))
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#define TCON (S3C_REG(0x1d50008))
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#define TCNTB0 (S3C_REG(0x1d5000c))
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#define TCMPB0 (S3C_REG(0x1d50010))
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#define TCNTO0 (S3C_REG(0x1d50014))
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#define TCNTB1 (S3C_REG(0x1d50018))
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#define TCMPB1 (S3C_REG(0x1d5001c))
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#define TCNTO1 (S3C_REG(0x1d50020))
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#define TCNTB2 (S3C_REG(0x1d50024))
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#define TCMPB2 (S3C_REG(0x1d50028))
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#define TCNTO2 (S3C_REG(0x1d5002c))
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#define TCNTB3 (S3C_REG(0x1d50030))
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#define TCMPB3 (S3C_REG(0x1d50034))
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#define TCNTO3 (S3C_REG(0x1d50038))
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#define TCNTB4 (S3C_REG(0x1d5003c))
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#define TCMPB4 (S3C_REG(0x1d50040))
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#define TCNTO4 (S3C_REG(0x1d50044))
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#define TCNTB5 (S3C_REG(0x1d50048))
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#define TCNTO5 (S3C_REG(0x1d5004c))
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/* IIC */
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#define IICCON (S3C_REG(0x1d60000))
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#define IICSTAT (S3C_REG(0x1d60004))
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#define IICADD (S3C_REG(0x1d60008))
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#define IICDS (S3C_REG(0x1d6000c))
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/* RTC */
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#define RTCCON (S3C_REGB(0x1d70040)
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#define RTCALM (S3C_REGB(0x1d70050)
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#define ALMSEC (S3C_REGB(0x1d70054)
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#define ALMMIN (S3C_REGB(0x1d70058)
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#define ALMHOUR (S3C_REGB(0x1d7005c)
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#define ALMDAY (S3C_REGB(0x1d70060)
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#define ALMMON (S3C_REGB(0x1d70064)
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#define ALMYEAR (S3C_REGB(0x1d70068)
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#define RTCRST (S3C_REGB(0x1d7006c)
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#define BCDSEC (S3C_REGB(0x1d70070)
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#define BCDMIN (S3C_REGB(0x1d70074)
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#define BCDHOUR (S3C_REGB(0x1d70078)
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#define BCDDAY (S3C_REGB(0x1d7007c)
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#define BCDDATE (S3C_REGB(0x1d70080)
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#define BCDMON (S3C_REGB(0x1d70084)
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#define BCDYEAR (S3C_REGB(0x1d70088)
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#define TICINT (S3C_REGB(0x1d7008c)
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/* Clock & Power management */
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#define PLLCON (S3C_REG(0x1d80000))
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#define CLKCON (S3C_REG(0x1d80004))
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#define CLKSLOW (S3C_REG(0x1d80008))
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#define LOCKTIME (S3C_REG(0x1d8000c))
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/* Interrupt */
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#define INTCON (S3C_REG(0x1e00000))
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#define INTPND (S3C_REG(0x1e00004))
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#define INTMOD (S3C_REG(0x1e00008))
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#define INTMSK (S3C_REG(0x1e0000c))
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#define I_PSLV (S3C_REG(0x1e00010))
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#define I_PMST (S3C_REG(0x1e00014))
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#define I_CSLV (S3C_REG(0x1e00018))
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#define I_CMST (S3C_REG(0x1e0001c))
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#define I_ISPR (S3C_REG(0x1e00020))
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#define I_ISPC (S3C_REG(0x1e00024))
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#define F_ISPR (S3C_REG(0x1e00038))
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#define F_ISPC (S3C_REG(0x1e0003c))
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/********************************/
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/* LCD Controller Registers */
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/********************************/
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#define LCDCON1 (S3C_REG(0x300000))
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#define LCDCON2 (S3C_REG(0x300004))
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#define LCDSADDR1 (S3C_REG(0x300008))
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#define LCDSADDR2 (S3C_REG(0x30000c))
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#define LCDSADDR3 (S3C_REG(0x300010))
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#define REDLUT (S3C_REG(0x300014))
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#define GREENLUT (S3C_REG(0x300018))
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#define BLUELUT (S3C_REG(0x30001c))
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#define DP1_2 (S3C_REG(0x300020))
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#define DP4_7 (S3C_REG(0x300024))
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#define DP3_5 (S3C_REG(0x300028))
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#define DP2_3 (S3C_REG(0x30002c))
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#define DP5_7 (S3C_REG(0x300030))
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#define DP3_4 (S3C_REG(0x300034))
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#define DP4_5 (S3C_REG(0x300038))
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#define DP6_7 (S3C_REG(0x30003c))
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#define LCDCON3 (S3C_REG(0x300040))
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#define DITHMODE (S3C_REG(0x300044))
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/* ZDMA0 */
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#define ZDCON0 (S3C_REG(0x1e80000))
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#define ZDISRC0 (S3C_REG(0x1e80004))
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#define ZDIDES0 (S3C_REG(0x1e80008))
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#define ZDICNT0 (S3C_REG(0x1e8000c))
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#define ZDCSRC0 (S3C_REG(0x1e80010))
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#define ZDCDES0 (S3C_REG(0x1e80014))
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#define ZDCCNT0 (S3C_REG(0x1e80018))
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/* ZDMA1 */
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#define ZDCON1 (S3C_REG(0x1e80020))
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#define ZDISRC1 (S3C_REG(0x1e80024))
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#define ZDIDES1 (S3C_REG(0x1e80028))
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#define ZDICNT1 (S3C_REG(0x1e8002c))
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#define ZDCSRC1 (S3C_REG(0x1e80030))
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#define ZDCDES1 (S3C_REG(0x1e80034))
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#define ZDCCNT1 (S3C_REG(0x1e80038))
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/* BDMA0 */
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#define BDCON0 (S3C_REG(0x1f80000))
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#define BDISRC0 (S3C_REG(0x1f80004))
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#define BDIDES0 (S3C_REG(0x1f80008))
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#define BDICNT0 (S3C_REG(0x1f8000c))
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#define BDCSRC0 (S3C_REG(0x1f80010))
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#define BDCDES0 (S3C_REG(0x1f80014))
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#define BDCCNT0 (S3C_REG(0x1f80018))
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/* BDMA1 */
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#define BDCON1 (S3C_REG(0x1f80020))
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#define BDISRC1 (S3C_REG(0x1f80024))
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#define BDIDES1 (S3C_REG(0x1f80028))
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#define BDICNT1 (S3C_REG(0x1f8002c))
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#define BDCSRC1 (S3C_REG(0x1f80030))
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#define BDCDES1 (S3C_REG(0x1f80034))
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#define BDCCNT1 (S3C_REG(0x1f80038))
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/*****************************/
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/* CPU Mode */
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/*****************************/
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#define USERMODE 0x10 /* User Mode(USR) */
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#define FIQMODE 0x11 /* Fast Interrupt Mode (FIQ) */
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#define IRQMODE 0x12 /* Interrupt Mode (IRQ) */
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#define SVCMODE 0x13 /* Supervisor Mode (SVC) */
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#define ABORTMODE 0x17 /* Abort Mode(ABT) */
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#define UNDEFMODE 0x1b /* Undefine Mode(UDF) */
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#define MODEMASK 0x1f /* Processor Mode Mask */
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#define NOINT 0xc0
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/*****************************/
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/* INT Define */
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/*****************************/
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#define INT_ADC 0x00
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#define INT_RTC 0x01
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#define INT_UTXD1 0x02
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#define INT_UTXD0 0x03
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#define INT_SIO 0x04
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#define INT_IIC 0x05
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#define INT_URXD1 0x06
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#define INT_URXD0 0x07
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#define INT_TIMER5 0x08
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#define INT_TIMER4 0x09
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#define INT_TIMER3 0x0A
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#define INT_TIMER2 0x0B
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#define INT_TIMER1 0x0C
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#define INT_TIMER0 0x0D
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#define INT_UERR01 0x0E
|
||
|
|
#define INT_WDT 0x1F
|
||
|
|
#define INT_BDMA1 0x10
|
||
|
|
#define INT_BDMA0 0x11
|
||
|
|
#define INT_ZDMA1 0x12
|
||
|
|
#define INT_ZDMA0 0x13
|
||
|
|
#define INT_TICK 0x14
|
||
|
|
#define INT_EINT4567 0x15
|
||
|
|
#define INT_EINT3 0x16
|
||
|
|
#define INT_EINT2 0x17
|
||
|
|
#define INT_EINT1 0x18
|
||
|
|
#define INT_EINT0 0x19
|
||
|
|
|
||
|
|
#define INT_GLOBAL 26
|
||
|
|
|
||
|
|
struct rt_hw_register
|
||
|
|
{
|
||
|
|
unsigned long r0;
|
||
|
|
unsigned long r1;
|
||
|
|
unsigned long r2;
|
||
|
|
unsigned long r3;
|
||
|
|
unsigned long r4;
|
||
|
|
unsigned long r5;
|
||
|
|
unsigned long r6;
|
||
|
|
unsigned long r7;
|
||
|
|
unsigned long r8;
|
||
|
|
unsigned long r9;
|
||
|
|
unsigned long r10;
|
||
|
|
unsigned long fp;
|
||
|
|
unsigned long ip;
|
||
|
|
unsigned long sp;
|
||
|
|
unsigned long lr;
|
||
|
|
unsigned long pc;
|
||
|
|
unsigned long cpsr;
|
||
|
|
unsigned long ORIG_r0;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*@}*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|