276 lines
6.1 KiB
ArmAsm
276 lines
6.1 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2006-08-31 Bernard first version
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*/
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/* Internal Memory Base Addresses */
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.equ FLASH_BASE, 0x00100000
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.equ RAM_BASE, 0x00200000
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/* Stack Configuration */
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.equ TOP_STACK, 0x00204000
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.equ UND_STACK_SIZE, 0x00000100
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.equ SVC_STACK_SIZE, 0x00000400
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.equ ABT_STACK_SIZE, 0x00000100
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.equ FIQ_STACK_SIZE, 0x00000100
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.equ IRQ_STACK_SIZE, 0x00000100
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.equ USR_STACK_SIZE, 0x00000004
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/* ARM architecture definitions */
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.equ MODE_USR, 0x10
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.equ MODE_FIQ, 0x11
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.equ MODE_IRQ, 0x12
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.equ MODE_SVC, 0x13
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.equ MODE_ABT, 0x17
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.equ MODE_UND, 0x1B
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.equ MODE_SYS, 0x1F
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.equ I_BIT, 0x80 /* when this bit is set, IRQ is disabled */
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.equ F_BIT, 0x40 /* when this bit is set, FIQ is disabled */
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.section .init, "ax"
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.code 32
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.align 0
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.globl _start
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_start:
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b reset
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ldr pc, _vector_undef
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ldr pc, _vector_swi
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ldr pc, _vector_pabt
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ldr pc, _vector_dabt
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nop /* reserved vector */
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ldr pc, _vector_irq
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ldr pc, _vector_fiq
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_vector_undef: .word vector_undef
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_vector_swi: .word vector_swi
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_vector_pabt: .word vector_pabt
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_vector_dabt: .word vector_dabt
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_vector_resv: .word vector_resv
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_vector_irq: .word vector_irq
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_vector_fiq: .word vector_fiq
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/*
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* rtthread bss start and end
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* which are defined in linker script
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*/
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.globl _bss_start
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_bss_start: .word __bss_start
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.globl _bss_end
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_bss_end: .word __bss_end
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/* the system entry */
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reset:
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/* disable watchdog */
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ldr r0, =0xFFFFFD40
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ldr r1, =0x00008000
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str r1, [r0, #0x04]
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/* enable the main oscillator */
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ldr r0, =0xFFFFFC00
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ldr r1, =0x00000601
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str r1, [r0, #0x20]
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/* wait for main oscillator to stabilize */
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moscs_loop:
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ldr r2, [r0, #0x68]
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ands r2, r2, #1
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beq moscs_loop
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/* set up the PLL */
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ldr r1, =0x00191C05
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str r1, [r0, #0x2C]
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/* wait for PLL to lock */
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pll_loop:
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ldr r2, [r0, #0x68]
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ands r2, r2, #0x04
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beq pll_loop
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/* select clock */
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ldr r1, =0x00000007
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str r1, [r0, #0x30]
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#ifdef __FLASH_BUILD__
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/* copy exception vectors into internal sram */
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/*
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mov r8, #RAM_BASE
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ldr r9, =_start
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ldmia r9!, {r0-r7}
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stmia r8!, {r0-r7}
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ldmia r9!, {r0-r6}
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stmia r8!, {r0-r6}
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*/
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#endif
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/* setup stack for each mode */
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ldr r0, =TOP_STACK
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/* set stack */
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/* undefined instruction mode */
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msr cpsr_c, #MODE_UND|I_BIT|F_BIT
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mov sp, r0
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sub r0, r0, #UND_STACK_SIZE
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/* abort mode */
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msr cpsr_c, #MODE_ABT|I_BIT|F_BIT
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mov sp, r0
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sub r0, r0, #ABT_STACK_SIZE
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/* FIQ mode */
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msr cpsr_c, #MODE_FIQ|I_BIT|F_BIT
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mov sp, r0
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sub r0, r0, #FIQ_STACK_SIZE
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/* IRQ mode */
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msr cpsr_c, #MODE_IRQ|I_BIT|F_BIT
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mov sp, r0
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sub r0, r0, #IRQ_STACK_SIZE
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/* supervisor mode */
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msr cpsr_c, #MODE_SVC|I_BIT|F_BIT
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mov sp, r0
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/* remap SRAM to 0x0000 */
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/*
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ldr r0, =0xFFFFFF00
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mov r1, #0x01
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str r1, [r0]
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*/
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/* mask all IRQs */
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ldr r1, =0xFFFFF124
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ldr r0, =0XFFFFFFFF
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str r0, [r1]
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/* copy .data to SRAM */
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ldr r1, =_sidata /* .data start in image */
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ldr r2, =_edata /* .data end in image */
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ldr r3, =_sdata /* sram data start */
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data_loop:
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ldr r0, [r1, #0]
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str r0, [r3]
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add r1, r1, #4
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add r3, r3, #4
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cmp r3, r2 /* check if data to clear */
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blo data_loop /* loop until done */
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup: .word rtthread_startup
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/* exception handlers */
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vector_undef: b vector_undef
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vector_swi : b vector_swi
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vector_pabt : b vector_pabt
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vector_dabt : b vector_dabt
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vector_resv : b vector_resv
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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vector_irq:
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stmfd sp!, {r0-r12,lr}
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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/*
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* if rt_thread_switch_interrupt_flag set, jump to
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* rt_hw_context_switch_interrupt_do and don't return
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*/
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ldr r0, =rt_thread_switch_interrupt_flag
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ldr r1, [r0]
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cmp r1, #1
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beq rt_hw_context_switch_interrupt_do
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ldmfd sp!, {r0-r12,lr}
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subs pc, lr, #4
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc,lr,#4
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/*
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* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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*/
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rt_hw_context_switch_interrupt_do:
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mov r1, #0 @ clear flag
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str r1, [r0]
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ldmfd sp!, {r0-r12,lr}@ reload saved registers
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stmfd sp!, {r0-r3} @ save r0-r3
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mov r1, sp
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add sp, sp, #16 @ restore sp
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sub r2, lr, #4 @ save old task's pc to r2
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mrs r3, spsr @ disable interrupt
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orr r0, r3, #I_BIT|F_BIT
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msr spsr_c, r0
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ldr r0, =.+8 @ switch to interrupted task's stack
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movs pc, r0
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stmfd sp!, {r2} @ push old task's pc
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stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4
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mov r4, r1 @ Special optimised code below
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mov r5, r3
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ldmfd r4!, {r0-r3}
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stmfd sp!, {r0-r3} @ push old task's r3-r0
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stmfd sp!, {r5} @ push old task's psr
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mrs r4, spsr
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stmfd sp!, {r4} @ push old task's spsr
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] @ store sp in preempted tasks's TCB
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6] @ get new task's stack pointer
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ldmfd sp!, {r4} @ pop new task's spsr
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msr SPSR_cxsf, r4
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ldmfd sp!, {r4} @ pop new task's psr
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msr CPSR_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc} @ pop new task's r0-r12,lr & pc
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