242 lines
8.3 KiB
Plaintext
242 lines
8.3 KiB
Plaintext
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/**************************************************************************************************
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Filename: cc2530-sb.xcl
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Revised: $Date: 2012-03-29 12:09:02 -0700 (Thu, 29 Mar 2012) $
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Revision: $Revision: 29943 $
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Description: This is a linker command line file for the IAR XLINK tool for the
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CC2530 SoC and Z-Stack sample applications where the General Options
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for location for constants and strings is "ROM mapped as data".
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This mapping is for applications that are to be loaded onto the
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TI CC2530/31 via the embedded serial boot loader.
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Copyright 2009-2010 Texas Instruments Incorporated. All rights reserved.
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IMPORTANT: Your use of this Software is limited to those specific rights
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granted under the terms of a software license agreement between the user
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who downloaded the software, his/her employer (which must be your employer)
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and Texas Instruments Incorporated (the "License"). You may not use this
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Software unless you agree to abide by the terms of the License. The License
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limits your use, and you acknowledge, that the Software may not be modified,
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copied or distributed unless embedded on a Texas Instruments microcontroller
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or used solely and exclusively in conjunction with a Texas Instruments radio
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frequency transceiver, which is integrated into your product. Other than for
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the foregoing purpose, you may not use, reproduce, copy, prepare derivative
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works of, modify, distribute, perform, display or sell this Software and/or
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its documentation for any purpose.
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YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE
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PROVIDED <20>AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
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INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE,
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NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL
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TEXAS INSTRUMENTS OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER CONTRACT,
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NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER
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LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES
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INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE
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OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT
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OF SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES
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(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
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Should you have any questions regarding your right to use this Software,
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contact Texas Instruments Incorporated at www.TI.com.
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**************************************************************************************************/
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Segment limits
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// --------------
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//
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//
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// XDATA available to the program.
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//
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// Reserving address 0x0 for NULL.
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-D_XDATA_START=0x0001 // The boot loader code depends on stack setting this byte to 0xCD,
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// which happens because it is the last byte of the XSTACK.
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-D_XDATA_END=0x1EFF
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//
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//
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// The 8052 IDATA is overlayed on the SoC XDATA space from 0x1F00-0x1FFF.
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//
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-D_IDATA_END=0xFF // Last address of Idata memory.
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//
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//
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// CODE
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//
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-D_CODE_START=0x2000
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-D_CODE_END=0x7FFF // Last address for ROOT bank.
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//
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-D_FIRST_BANK_ADDR=0x10000
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//
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//
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//
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// Special SFRs
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// ------------
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//
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// Register bank setup
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//
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-D?REGISTER_BANK=0 // Default register bank (0,1,2,3).
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-D_REGISTER_BANK_START=0 // Start address for default register bank (00,08,10,18).
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//
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//
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// PDATA page setup
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//
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-D?PBANK_NUMBER=00 // High byte of 16-bit address to the PDATA area.
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//
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//
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// Virtual register setup
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// ----------------------
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//
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-D_BREG_START=0x00 // The bit address where the BREG segments starts.
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// Must be placed on: _BREG_START%8=0 where _BREG_START <= 0x78.
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-D?VB=0x20 // ?VB is used when referencing BREG as whole byte.
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// Must be placed on: ?VB=0x20+_BREG_START/8.
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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// IDATA memory
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//
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// Setup "bit" segments (only for '__no_init bool' variables).
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-Z(BIT)BREG=_BREG_START
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-Z(BIT)BIT_N=0-7F
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-Z(DATA)REGISTERS+8=_REGISTER_BANK_START
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-Z(DATA)BDATA_Z,BDATA_N,BDATA_I=20-2F
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-Z(DATA)VREG+_NR_OF_VIRTUAL_REGISTERS=08-7F
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-Z(DATA)PSP,XSP=08-7F
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-Z(DATA)DOVERLAY=08-7F
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-Z(DATA)DATA_I,DATA_Z,DATA_N=08-7F
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-U(IDATA)0-7F=(DATA)0-7F
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-Z(IDATA)IDATA_I,IDATA_Z,IDATA_N=08-_IDATA_END
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-Z(IDATA)ISTACK+_IDATA_STACK_SIZE#08-_IDATA_END
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-Z(IDATA)IOVERLAY=08-FF
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////////////////////////////////////////////////////////////////////////////////
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//
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// ROM memory
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//
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//
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// The following segments *must* be placed in the root bank. The order of
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// placement also matters for these segments, which is why we use the -Z
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// placement directive.
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//
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-Z(CODE)INTVEC=_CODE_START
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-Z(CODE)CHECKSUM=0x2090-0x2091
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-Z(CODE)CRC_SHDW=0x2092-0x2093
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-Z(CODE)BIT_ID,BDATA_ID,DATA_ID,IDATA_ID,IXDATA_ID,PDATA_ID,PDATA_Z,XDATA_ID=_CODE_START-_CODE_END
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//
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// Sleep PCON instruction must be 4-byte aligned.
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//
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-D_SLEEP_CODE_SPACE_START=(_CODE_END-7)
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-D_SLEEP_CODE_SPACE_END=(_CODE_END)
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-Z(CODE)SLEEP_CODE=_SLEEP_CODE_SPACE_START-_SLEEP_CODE_SPACE_END
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//
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// The following segments *must* be placed in the root bank, but the order
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// of placement within the root bank is not important, which is why we use the
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// -P directive here.
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//
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-P(CODE)CSTART,BANK_RELAYS,RCODE,DIFUNCT,NEAR_CODE=_CODE_START-_CODE_END
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//
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// Setup for constants located in code memory:
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//
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-P(CODE)CODE_C=_CODE_START-_CODE_END
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//
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// Define segments for const data in flash.
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// First the segment with addresses as used by the program (flash mapped as XDATA)
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-P(CONST)XDATA_ROM_C=0x8000-0xFFFF
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//
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// Then the segment with addresses as put in the hex file (flash bank 1)
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-P(CODE)XDATA_ROM_C_FLASH=0x18000-0x1FFFF
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//
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// Finally link these segments (XDATA_ROM_C_FLASH is the initializer segment for XDATA_ROM_C,
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// we map the flash in the XDATA address range instead of copying the data to RAM)
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-QXDATA_ROM_C=XDATA_ROM_C_FLASH
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//
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// The directive below ensures that the remaining space in the root bank gets
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// filled, then starts filling the banks.
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//
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-P(CODE)BANKED_CODE=_CODE_START-_CODE_END,0x18000-0x1FFFF,0x28000-0x2FFFF,0x38000-0x3FFFF,\
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0x48000-0x4FFFF,0x58000-0x5FFFF,0x68000-0x6FFFF,0x78000-0x7C7FF
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////////////////////////////////////////////////////////////////////////////////
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//
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// XDATA memory
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//
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-Z(XDATA)XSTACK+_XDATA_STACK_SIZE=_XDATA_START-_XDATA_END
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-Z(XDATA)XDATA_Z,XDATA_I=_XDATA_START-_XDATA_END
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-P(XDATA)XDATA_N=_XDATA_START-_XDATA_END
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-cx51
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////////////////////////////////////////////////////////////////////////////////
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//
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// Texas Instruments device specific
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// =================================
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//
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//
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// Layout of CODE banks
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// -------------------
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//
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//-D_BANK0_START=0x08000
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//-D_BANK0_END=0x0FFFF
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//
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//-D_BANK1_START=0x18000
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//-D_BANK1_END=0x1FFFF
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//
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//-D_BANK2_START=0x28000
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//-D_BANK2_END=0x2FFFF
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//
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//-D_BANK3_START=0x38000
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//-D_BANK3_END=0x3FFFF
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//
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//-D_BANK4_START=0x48000
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//-D_BANK4_END=0x4FFFF
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//
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//-D_BANK5_START=0x58000
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//-D_BANK5_END=0x5FFFF
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//
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//-D_BANK6_START=0x68000
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//-D_BANK6_END=0x6FFFF
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//
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//-D_BANK7_START=0x78000
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//-D_BANK7_END=0x7FFFF
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//
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//
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// Include these two lines when generating a .hex file for banked code model:
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//-M(CODE)[(_CODEBANK_START+_FIRST_BANK_ADDR)-(_CODEBANK_END+_FIRST_BANK_ADDR)]*\
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//_NR_OF_BANKS+_FIRST_BANK_ADDR=0x8000
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//
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//
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// Internal flash used for NV address space: reserving 6 pages.
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// NV memory segment size must coincide with page declarations in "hal_board_cfg.h" file.
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//
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-D_ZIGNV_ADDRESS_SPACE_START=(((_NR_OF_BANKS+1)*_FIRST_BANK_ADDR)-0x3800)
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-D_ZIGNV_ADDRESS_SPACE_END=(_ZIGNV_ADDRESS_SPACE_START+0x2FFF)
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-Z(CODE)ZIGNV_ADDRESS_SPACE=_ZIGNV_ADDRESS_SPACE_START-_ZIGNV_ADDRESS_SPACE_END
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Skip boot code, CRC/shadow & NV pages when calculating the CRC.
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//
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-J2,crc16,=2000-208F,2094-7C7FF
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//
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// Fill code gaps with 0xFFFF so that the CRC can be verified programatically.
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-HFFFF
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//
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////////////////////////////////////////////////////////////////////////////////
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