62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
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#ifndef _PPC4xx_UIC_H_
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#define _PPC4xx_UIC_H_
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/*
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* Define the number of UIC's
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*/
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#define UIC_MAX 1
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#define IRQ_MAX UIC_MAX * 32
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/* UIC0 dcr base address */
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#define UIC0_DCR_BASE 0xc0
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/*
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* UIC register
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*/
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#define UIC_SR 0x0 /* UIC status */
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#define UIC_ER 0x2 /* UIC enable */
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#define UIC_CR 0x3 /* UIC critical */
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#define UIC_PR 0x4 /* UIC polarity */
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#define UIC_TR 0x5 /* UIC triggering */
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#define UIC_MSR 0x6 /* UIC masked status */
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#define UIC_VR 0x7 /* UIC vector */
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#define UIC_VCR 0x8 /* UIC vector configuration */
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#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
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#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
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#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
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#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
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#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
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#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
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#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
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#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
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/* The following is for compatibility with 405 code */
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#define uicsr uic0sr
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#define uicer uic0er
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#define uiccr uic0cr
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#define uicpr uic0pr
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#define uictr uic0tr
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#define uicmsr uic0msr
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#define uicvr uic0vr
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#define uicvcr uic0vcr
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/* the interrupt vector definitions */
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#define VECNUM_MAL_SERR 10
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#define VECNUM_MAL_TXEOB 11
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#define VECNUM_MAL_RXEOB 12
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#define VECNUM_MAL_TXDE 13
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#define VECNUM_MAL_RXDE 14
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#define VECNUM_ETH0 15
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#define VECNUM_ETH1_OFFS 2
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#define VECNUM_EIRQ6 29
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/*
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* Mask definitions (used for example in 4xx_enet.c)
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*/
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#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
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/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
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#define UIC_NR(vec) ((vec) >> 5)
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#endif /* _PPC4xx_UIC_H_ */
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