71 lines
1.5 KiB
ArmAsm
71 lines
1.5 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-12-04 Jiaxun Yang Initial version
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* 2020-07-26 lizhirui Add xtlb exception entry
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include <mips.h>
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.section ".exc_vectors", "ax"
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.extern tlb_refill_handler
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.extern cache_error_handler
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.extern mips_irq_handle
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/* 0x0 - TLB refill handler */
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.global tlb_refill_exception
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.type tlb_refill_exception,@function
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ebase_start:
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tlb_refill_exception:
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b _general_exception_handler
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nop
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/* 0x080 - XTLB refill handler */
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.org ebase_start + 0x080
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b _general_exception_handler
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nop
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/* 0x100 - Cache error handler */
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.org ebase_start + 0x100
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j cache_error_handler
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nop
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/* 0x180 - Exception/Interrupt handler */
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.global general_exception
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.type general_exception,@function
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.org ebase_start + 0x180
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general_exception:
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b _general_exception_handler
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nop
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/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
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.global irq_exception
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.type irq_exception,@function
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.org ebase_start + 0x200
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irq_exception:
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b _general_exception_handler
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nop
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/* general exception handler */
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_general_exception_handler:
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.set noreorder
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PTR_LA k0, mips_irq_handle
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jr k0
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nop
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.set reorder
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/* interrupt handler */
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_irq_handler:
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.set noreorder
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PTR_LA k0, mips_irq_handle
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jr k0
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nop
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.set reorder
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