387 lines
9.1 KiB
ArmAsm
387 lines
9.1 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2006-03-13 Bernard first version
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* 2006-10-05 Alsor.Z for s3c2440 initialize
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* 2008-01-29 Yi.Qiu for QEMU emulator
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*/
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#define CONFIG_STACKSIZE 512
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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.equ USERMODE, 0x10
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.equ FIQMODE, 0x11
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.equ IRQMODE, 0x12
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.equ SVCMODE, 0x13
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.equ ABORTMODE, 0x17
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.equ UNDEFMODE, 0x1b
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.equ MODEMASK, 0x1f
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.equ NOINT, 0xc0
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.equ RAM_BASE, 0x00000000 /*Start address of RAM */
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.equ ROM_BASE, 0x30000000 /*Start address of Flash */
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.equ MPLLCON, 0x4c000004 /*Mpll control register */
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.equ M_MDIV, 0x20
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.equ M_PDIV, 0x4
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.equ M_SDIV, 0x2
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.equ INTMSK, 0x4a000008
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.equ INTSUBMSK, 0x4a00001c
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.equ WTCON, 0x53000000
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.equ LOCKTIME, 0x4c000000
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.equ CLKDIVN, 0x4c000014 /*Clock divider control */
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.equ GPHCON, 0x56000070 /*Port H control */
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.equ GPHUP, 0x56000078 /*Pull-up control H */
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.equ BWSCON, 0x48000000 /*Bus width & wait status */
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.equ BANKCON0, 0x48000004 /*Boot ROM control */
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.equ BANKCON1, 0x48000008 /*BANK1 control */
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.equ BANKCON2, 0x4800000c /*BANK2 cControl */
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.equ BANKCON3, 0x48000010 /*BANK3 control */
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.equ BANKCON4, 0x48000014 /*BANK4 control */
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.equ BANKCON5, 0x48000018 /*BANK5 control */
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.equ BANKCON6, 0x4800001c /*BANK6 control */
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.equ BANKCON7, 0x48000020 /*BANK7 control */
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.equ REFRESH, 0x48000024 /*DRAM/SDRAM efresh */
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.equ BANKSIZE, 0x48000028 /*Flexible Bank Size */
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.equ MRSRB6, 0x4800002c /*Mode egister set for SDRAM*/
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.equ MRSRB7, 0x48000030 /*Mode egister set for SDRAM*/
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/*
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*************************************************************************
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*
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* Jump vector table
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*
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*************************************************************************
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*/
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.section .init, "ax"
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.code 32
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.globl _start
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_start:
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b reset
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ldr pc, _vector_undef
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ldr pc, _vector_swi
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ldr pc, _vector_pabt
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ldr pc, _vector_dabt
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ldr pc, _vector_resv
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ldr pc, _vector_irq
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ldr pc, _vector_fiq
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_vector_undef: .word vector_undef
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_vector_swi: .word vector_swi
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_vector_pabt: .word vector_pabt
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_vector_dabt: .word vector_dabt
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_vector_resv: .word vector_resv
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_vector_irq: .word vector_irq
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_vector_fiq: .word vector_fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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* relocate armboot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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_TEXT_BASE:
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.word TEXT_BASE
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/*
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* rtthread kernel start and end
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* which are defined in linker script
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*/
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.globl _rtthread_start
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_rtthread_start:
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.word _start
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.globl _rtthread_end
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_rtthread_end:
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.word _end
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/*
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* rtthread bss start and end which are defined in linker script
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word __bss_end
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word _irq_stack_start + 1024
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word _fiq_stack_start + 1024
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.globl UNDEFINED_STACK_START
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UNDEFINED_STACK_START:
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.word _undefined_stack_start + CONFIG_STACKSIZE
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.globl ABORT_STACK_START
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ABORT_STACK_START:
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.word _abort_stack_start + CONFIG_STACKSIZE
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.globl _STACK_START
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_STACK_START:
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.word _svc_stack_start + 4096
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/* ----------------------------------entry------------------------------*/
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reset:
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/* set the cpu to SVC32 mode */
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mrs r0,cpsr
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bic r0,r0,#MODEMASK
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orr r0,r0,#SVCMODE
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msr cpsr,r0
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/* watch dog disable */
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ldr r0,=WTCON
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ldr r1,=0x0
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str r1,[r0]
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/* mask all IRQs by clearing all bits in the INTMRs */
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ldr r1, =INTMSK
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ldr r0, =0xffffffff
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str r0, [r1]
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ldr r1, =INTSUBMSK
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ldr r0, =0x7fff /*all sub interrupt disable */
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str r0, [r1]
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/* set interrupt vector */
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ldr r0, _load_address
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mov r1, #0x0 /* target address */
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add r2, r0, #0x20 /* size, 32bytes */
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copy_loop:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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ble copy_loop
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/* setup stack */
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bl stack_setup
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup:
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.word rtthread_startup
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#if defined (__FLASH_BUILD__)
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_load_address:
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.word ROM_BASE + _TEXT_BASE
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#else
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_load_address:
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.word RAM_BASE + _TEXT_BASE
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#endif
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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/* exception handlers */
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.align 5
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vector_undef:
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} /* Calling r0-r12 */
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ /* Calling SP, LR */
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str lr, [r8, #0] /* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] /* Save CPSR */
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str r0, [r8, #8] /* Save OLD_R0 */
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mov r0, sp
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bl rt_hw_trap_udef
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.align 5
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vector_swi:
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bl rt_hw_trap_swi
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.align 5
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vector_pabt:
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bl rt_hw_trap_pabt
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.align 5
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vector_dabt:
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} /* Calling r0-r12 */
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ /* Calling SP, LR */
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str lr, [r8, #0] /* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] /* Save CPSR */
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str r0, [r8, #8] /* Save OLD_R0 */
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mov r0, sp
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bl rt_hw_trap_dabt
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.align 5
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vector_resv:
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bl rt_hw_trap_resv
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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vector_irq:
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stmfd sp!, {r0-r12,lr}
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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/* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */
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ldr r0, =rt_thread_switch_interrupt_flag
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ldr r1, [r0]
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cmp r1, #1
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beq _interrupt_thread_switch
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ldmfd sp!, {r0-r12,lr}
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subs pc, lr, #4
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.align 5
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc,lr,#4
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_interrupt_thread_switch:
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mov r1, #0 /* clear rt_thread_switch_interrupt_flag*/
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str r1, [r0]
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ldmfd sp!, {r0-r12,lr} /* reload saved registers */
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stmfd sp!, {r0-r3} /* save r0-r3 */
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mov r1, sp
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add sp, sp, #16 /* restore sp */
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sub r2, lr, #4 /* save old task's pc to r2 */
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mrs r3, spsr /* disable interrupt */
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orr r0, r3, #NOINT
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msr spsr_c, r0
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ldr r0, =.+8 /* switch to interrupted task's stack*/
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movs pc, r0
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stmfd sp!, {r2} /* push old task's pc */
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stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */
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mov r4, r1 /* Special optimised code below */
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mov r5, r3
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ldmfd r4!, {r0-r3}
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stmfd sp!, {r0-r3} /* push old task's r3-r0 */
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stmfd sp!, {r5} /* push old task's psr */
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mrs r4, spsr
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stmfd sp!, {r4} /* push old task's spsr */
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] /* store sp in preempted tasks's TCB*/
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6] /* get new task's stack pointer */
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ldmfd sp!, {r4} /* pop new task's spsr */
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msr SPSR_cxsf, r4
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ldmfd sp!, {r4} /* pop new task's psr */
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msr CPSR_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
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stack_setup:
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mrs r0, cpsr
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bic r0, r0, #MODEMASK
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orr r1, r0, #UNDEFMODE|NOINT
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msr cpsr_cxsf, r1 /* undef mode */
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ldr sp, UNDEFINED_STACK_START
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orr r1,r0,#ABORTMODE|NOINT
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msr cpsr_cxsf,r1 /* abort mode */
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ldr sp, ABORT_STACK_START
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orr r1,r0,#IRQMODE|NOINT
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msr cpsr_cxsf,r1 /* IRQ mode */
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ldr sp, IRQ_STACK_START
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orr r1,r0,#FIQMODE|NOINT
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msr cpsr_cxsf,r1 /* FIQ mode */
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ldr sp, FIQ_STACK_START
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bic r0,r0,#MODEMASK
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orr r1,r0,#SVCMODE|NOINT
|
||
|
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msr cpsr_cxsf,r1 /* SVC mode */
|
||
|
|
|
||
|
|
ldr sp, _STACK_START
|
||
|
|
|
||
|
|
/* USER mode is not initialized. */
|
||
|
|
mov pc,lr /* The LR register may be not valid for the mode changes.*/
|
||
|
|
|
||
|
|
/*/*}*/
|
||
|
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|