301 lines
9.1 KiB
C
301 lines
9.1 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-20 Bernard first version
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* 2014-04-03 Grissiom many enhancements
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* 2018-11-22 Jesven add rt_hw_ipi_send()
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* add rt_hw_ipi_handler_install()
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "gic.h"
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#include "cp15.h"
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struct arm_gic
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{
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rt_uint32_t offset; /* the first interrupt index in the vector table */
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rt_uint32_t dist_hw_base; /* the base address of the gic distributor */
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rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */
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};
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/* 'ARM_GIC_MAX_NR' is the number of cores */
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static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
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#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00)
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#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04)
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#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08)
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#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c)
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#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10)
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#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14)
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#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18)
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#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000)
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#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004)
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#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4)
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#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4)
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#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4)
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#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4)
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#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4)
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#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4)
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#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4)
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#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4)
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#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4)
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#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
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#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00)
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#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
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#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8)
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static unsigned int _gic_max_irq;
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int arm_gic_get_active_irq(rt_uint32_t index)
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{
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int irq;
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
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irq += _gic_table[index].offset;
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return irq;
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}
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void arm_gic_ack(rt_uint32_t index, int irq)
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{
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rt_uint32_t mask = 1 << (irq % 32);
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = irq - _gic_table[index].offset;
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RT_ASSERT(irq >= 0);
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GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
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GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
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}
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void arm_gic_mask(rt_uint32_t index, int irq)
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{
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rt_uint32_t mask = 1 << (irq % 32);
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = irq - _gic_table[index].offset;
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RT_ASSERT(irq >= 0);
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GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
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}
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void arm_gic_clear_pending(rt_uint32_t index, int irq)
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{
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rt_uint32_t mask = 1 << (irq % 32);
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = irq - _gic_table[index].offset;
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RT_ASSERT(irq >= 0);
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GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
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}
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void arm_gic_clear_active(rt_uint32_t index, int irq)
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{
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rt_uint32_t mask = 1 << (irq % 32);
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = irq - _gic_table[index].offset;
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RT_ASSERT(irq >= 0);
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GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
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}
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/* Set up the cpu mask for the specific interrupt */
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void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
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{
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rt_uint32_t old_tgt;
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = irq - _gic_table[index].offset;
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RT_ASSERT(irq >= 0);
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old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
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old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
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old_tgt |= cpumask << ((irq % 4)*8);
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GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
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}
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void arm_gic_umask(rt_uint32_t index, int irq)
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{
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rt_uint32_t mask = 1 << (irq % 32);
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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irq = irq - _gic_table[index].offset;
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RT_ASSERT(irq >= 0);
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GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
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}
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void arm_gic_dump_type(rt_uint32_t index)
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{
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unsigned int gic_type;
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gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
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rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
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(GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
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_gic_table[index].dist_hw_base,
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_gic_max_irq,
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gic_type & (1 << 10) ? "has" : "no",
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gic_type);
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}
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void arm_gic_dump(rt_uint32_t index)
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{
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unsigned int i, k;
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k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
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rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
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rt_kprintf("--- hw mask ---\n");
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for (i = 0; i < _gic_max_irq / 32; i++)
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{
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rt_kprintf("0x%08x, ",
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GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
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i * 32));
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}
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rt_kprintf("\n--- hw pending ---\n");
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for (i = 0; i < _gic_max_irq / 32; i++)
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{
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rt_kprintf("0x%08x, ",
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GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
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i * 32));
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}
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rt_kprintf("\n--- hw active ---\n");
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for (i = 0; i < _gic_max_irq / 32; i++)
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{
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rt_kprintf("0x%08x, ",
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GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
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i * 32));
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}
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rt_kprintf("\n");
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}
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
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#endif
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int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
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{
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unsigned int gic_type, i;
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rt_uint32_t cpumask = 1 << 0;
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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_gic_table[index].dist_hw_base = dist_base;
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_gic_table[index].offset = irq_start;
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/* Find out how many interrupts are supported. */
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gic_type = GIC_DIST_TYPE(dist_base);
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_gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
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/*
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* The GIC only supports up to 1020 interrupt sources.
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* Limit this to either the architected maximum, or the
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* platform maximum.
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*/
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if (_gic_max_irq > 1020)
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_gic_max_irq = 1020;
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if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
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_gic_max_irq = ARM_GIC_NR_IRQS;
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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cpumask |= cpumask << 24;
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GIC_DIST_CTRL(dist_base) = 0x0;
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/* Set all global interrupts to be level triggered, active low. */
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for (i = 32; i < _gic_max_irq; i += 16)
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GIC_DIST_CONFIG(dist_base, i) = 0x0;
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/* Set all global interrupts to this CPU only. */
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for (i = 32; i < _gic_max_irq; i += 4)
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GIC_DIST_TARGET(dist_base, i) = cpumask;
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/* Set priority on all interrupts. */
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for (i = 0; i < _gic_max_irq; i += 4)
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GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
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/* Disable all interrupts. */
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for (i = 0; i < _gic_max_irq; i += 32)
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GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
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#if 0
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/* All interrupts defaults to IGROUP1(IRQ). */
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for (i = 0; i < _gic_max_irq; i += 32)
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GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
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#endif
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for (i = 0; i < _gic_max_irq; i += 32)
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GIC_DIST_IGROUP(dist_base, i) = 0;
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/* Enable group0 and group1 interrupt forwarding. */
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GIC_DIST_CTRL(dist_base) = 0x01;
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return 0;
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}
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int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
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{
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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_gic_table[index].cpu_hw_base = cpu_base;
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GIC_CPU_PRIMASK(cpu_base) = 0xf0;
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GIC_CPU_BINPOINT(cpu_base) = 0x7;
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/* Enable CPU interrupt */
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GIC_CPU_CTRL(cpu_base) = 0x01;
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return 0;
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}
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void arm_gic_set_group(rt_uint32_t index, int vector, int group)
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{
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/* As for GICv2, there are only group0 and group1. */
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RT_ASSERT(group <= 1);
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RT_ASSERT(vector < _gic_max_irq);
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if (group == 0)
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{
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GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
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vector) &= ~(1 << (vector % 32));
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}
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else if (group == 1)
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{
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GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
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vector) |= (1 << (vector % 32));
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}
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}
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#ifdef RT_USING_SMP
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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{
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/* note: ipi_vector maybe different with irq_vector */
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GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector;
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}
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#endif
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#ifdef RT_USING_SMP
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void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
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{
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/* note: ipi_vector maybe different with irq_vector */
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rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
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}
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#endif
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