319 lines
10 KiB
C
319 lines
10 KiB
C
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/**
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******************************************************************************
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* @file stm32f1xx_ll_wwdg.h
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* @author MCD Application Team
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* @brief Header file of WWDG LL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32F1xx_LL_WWDG_H
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#define STM32F1xx_LL_WWDG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx.h"
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/** @addtogroup STM32F1xx_LL_Driver
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* @{
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*/
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#if defined (WWDG)
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/** @defgroup WWDG_LL WWDG
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
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* @{
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*/
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/** @defgroup WWDG_LL_EC_IT IT Defines
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* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
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* @{
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*/
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#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
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/**
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* @}
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*/
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/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
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* @{
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*/
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#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
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#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
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#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
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#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
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* @{
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*/
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/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
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* @{
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*/
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/**
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* @brief Write a value in WWDG register
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* @param __INSTANCE__ WWDG Instance
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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/**
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* @brief Read a value in WWDG register
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* @param __INSTANCE__ WWDG Instance
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
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* @{
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*/
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/** @defgroup WWDG_LL_EF_Configuration Configuration
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* @{
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*/
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/**
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* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
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* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
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* then it cannot be disabled again except by a reset.
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* This bit is set by software and only cleared by hardware after a reset.
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* When WDGA = 1, the watchdog can generate a reset.
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* @rmtoll CR WDGA LL_WWDG_Enable
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* @param WWDGx WWDG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
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{
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SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
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}
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/**
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* @brief Checks if Window Watchdog is enabled
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* @rmtoll CR WDGA LL_WWDG_IsEnabled
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* @param WWDGx WWDG Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
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{
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return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
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}
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/**
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* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
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* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
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* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
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* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
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* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
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* @rmtoll CR T LL_WWDG_SetCounter
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* @param WWDGx WWDG Instance
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* @param Counter 0..0x7F (7 bit counter value)
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* @retval None
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*/
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__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
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{
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MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
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}
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/**
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* @brief Return current Watchdog Counter Value (7 bits counter value)
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* @rmtoll CR T LL_WWDG_GetCounter
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* @param WWDGx WWDG Instance
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* @retval 7 bit Watchdog Counter value
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*/
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__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
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{
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return (READ_BIT(WWDGx->CR, WWDG_CR_T));
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}
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/**
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* @brief Set the time base of the prescaler (WDGTB).
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* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
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* is decremented every (4096 x 2expWDGTB) PCLK cycles
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* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
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* @param WWDGx WWDG Instance
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* @param Prescaler This parameter can be one of the following values:
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* @arg @ref LL_WWDG_PRESCALER_1
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* @arg @ref LL_WWDG_PRESCALER_2
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* @arg @ref LL_WWDG_PRESCALER_4
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* @arg @ref LL_WWDG_PRESCALER_8
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* @retval None
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*/
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__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
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{
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MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
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}
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/**
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* @brief Return current Watchdog Prescaler Value
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* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
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* @param WWDGx WWDG Instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_WWDG_PRESCALER_1
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* @arg @ref LL_WWDG_PRESCALER_2
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* @arg @ref LL_WWDG_PRESCALER_4
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* @arg @ref LL_WWDG_PRESCALER_8
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*/
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__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
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{
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return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
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}
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/**
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* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
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* @note This window value defines when write in the WWDG_CR register
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* to program Watchdog counter is allowed.
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* Watchdog counter value update must occur only when the counter value
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* is lower than the Watchdog window register value.
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* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
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* (in the control register) is refreshed before the downcounter has reached
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* the watchdog window register value.
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* Physically is possible to set the Window lower then 0x40 but it is not recommended.
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* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
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* @rmtoll CFR W LL_WWDG_SetWindow
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* @param WWDGx WWDG Instance
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* @param Window 0x00..0x7F (7 bit Window value)
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* @retval None
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*/
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__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
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{
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MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
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}
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/**
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* @brief Return current Watchdog Window Value (7 bits value)
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* @rmtoll CFR W LL_WWDG_GetWindow
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* @param WWDGx WWDG Instance
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* @retval 7 bit Watchdog Window value
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*/
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__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
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{
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return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
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}
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/**
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* @}
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*/
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/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
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* @{
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*/
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/**
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* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
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* @note This bit is set by hardware when the counter has reached the value 0x40.
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* It must be cleared by software by writing 0.
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* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
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* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
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* @param WWDGx WWDG Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
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{
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return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
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}
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/**
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* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
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* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
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* @param WWDGx WWDG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
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{
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WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
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}
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/**
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* @}
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*/
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/** @defgroup WWDG_LL_EF_IT_Management IT_Management
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* @{
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*/
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/**
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* @brief Enable the Early Wakeup Interrupt.
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* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
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* This interrupt is only cleared by hardware after a reset
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* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
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* @param WWDGx WWDG Instance
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* @retval None
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*/
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__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
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{
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SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
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}
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/**
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* @brief Check if Early Wakeup Interrupt is enabled
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* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
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* @param WWDGx WWDG Instance
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
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{
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return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* WWDG */
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32F1xx_LL_WWDG_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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