399 lines
10 KiB
C
399 lines
10 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-27 zylx first version
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*/
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#include "board.h"
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#include<rtthread.h>
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#include<rtdevice.h>
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#include "drv_qspi.h"
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#include "drv_config.h"
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#ifdef RT_USING_QSPI
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#define DRV_DEBUG
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#define LOG_TAG "drv.qspi"
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#include <drv_log.h>
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#if defined(BSP_USING_QSPI)
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struct stm32_hw_spi_cs
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{
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uint16_t Pin;
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};
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struct stm32_qspi_bus
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{
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QSPI_HandleTypeDef QSPI_Handler;
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char *bus_name;
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#ifdef BSP_QSPI_USING_DMA
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DMA_HandleTypeDef hdma_quadspi;
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#endif
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};
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struct rt_spi_bus _qspi_bus1;
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struct stm32_qspi_bus _stm32_qspi_bus;
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static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configuration *qspi_cfg)
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{
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int result = RT_EOK;
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unsigned int i = 1;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(qspi_cfg != RT_NULL);
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struct rt_spi_configuration *cfg = &qspi_cfg->parent;
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struct stm32_qspi_bus *qspi_bus = device->parent.bus->parent.user_data;
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rt_memset(&qspi_bus->QSPI_Handler, 0, sizeof(qspi_bus->QSPI_Handler));
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QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG;
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qspi_bus->QSPI_Handler = QSPI_Handler_config;
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while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1))
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{
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i++;
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if (i == 255)
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{
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LOG_E("QSPI init failed, QSPI frequency(%d) is too low.", cfg->max_hz);
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return -RT_ERROR;
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}
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}
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/* 80/(1+i) */
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qspi_bus->QSPI_Handler.Init.ClockPrescaler = i;
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if (!(cfg->mode & RT_SPI_CPOL))
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{
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/* QSPI MODE0 */
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qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_0;
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}
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else
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{
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/* QSPI MODE3 */
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qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_3;
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}
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/* flash size */
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qspi_bus->QSPI_Handler.Init.FlashSize = POSITION_VAL(qspi_cfg->medium_size) - 1;
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result = HAL_QSPI_Init(&qspi_bus->QSPI_Handler);
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if (result == HAL_OK)
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{
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LOG_D("qspi init success!");
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}
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else
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{
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LOG_E("qspi init failed (%d)!", result);
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}
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#ifdef BSP_QSPI_USING_DMA
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/* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */
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HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(QSPI_IRQn);
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HAL_NVIC_SetPriority(QSPI_DMA_IRQ, 0, 0);
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HAL_NVIC_EnableIRQ(QSPI_DMA_IRQ);
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/* init QSPI DMA */
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if(QSPI_DMA_RCC == RCC_AHB1ENR_DMA1EN)
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{
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__HAL_RCC_DMA1_CLK_ENABLE();
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}
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else
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{
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__HAL_RCC_DMA2_CLK_ENABLE();
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}
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HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
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DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG;
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qspi_bus->hdma_quadspi = hdma_quadspi_config;
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if (HAL_DMA_Init(&qspi_bus->hdma_quadspi) != HAL_OK)
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{
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LOG_E("qspi dma init failed (%d)!", result);
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}
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__HAL_LINKDMA(&qspi_bus->QSPI_Handler, hdma, qspi_bus->hdma_quadspi);
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#endif /* BSP_QSPI_USING_DMA */
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return result;
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}
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static void qspi_send_cmd(struct stm32_qspi_bus *qspi_bus, struct rt_qspi_message *message)
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{
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RT_ASSERT(qspi_bus != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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QSPI_CommandTypeDef Cmdhandler;
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/* set QSPI cmd struct */
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Cmdhandler.Instruction = message->instruction.content;
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Cmdhandler.Address = message->address.content;
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Cmdhandler.DummyCycles = message->dummy_cycles;
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if (message->instruction.qspi_lines == 0)
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{
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Cmdhandler.InstructionMode = QSPI_INSTRUCTION_NONE;
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}
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else if (message->instruction.qspi_lines == 1)
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{
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Cmdhandler.InstructionMode = QSPI_INSTRUCTION_1_LINE;
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}
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else if (message->instruction.qspi_lines == 2)
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{
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Cmdhandler.InstructionMode = QSPI_INSTRUCTION_2_LINES;
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}
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else if (message->instruction.qspi_lines == 4)
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{
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Cmdhandler.InstructionMode = QSPI_INSTRUCTION_4_LINES;
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}
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if (message->address.qspi_lines == 0)
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{
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Cmdhandler.AddressMode = QSPI_ADDRESS_NONE;
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}
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else if (message->address.qspi_lines == 1)
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{
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Cmdhandler.AddressMode = QSPI_ADDRESS_1_LINE;
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}
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else if (message->address.qspi_lines == 2)
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{
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Cmdhandler.AddressMode = QSPI_ADDRESS_2_LINES;
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}
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else if (message->address.qspi_lines == 4)
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{
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Cmdhandler.AddressMode = QSPI_ADDRESS_4_LINES;
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}
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if (message->address.size == 24)
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{
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Cmdhandler.AddressSize = QSPI_ADDRESS_24_BITS;
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}
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else
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{
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Cmdhandler.AddressSize = QSPI_ADDRESS_32_BITS;
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}
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if (message->qspi_data_lines == 0)
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{
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Cmdhandler.DataMode = QSPI_DATA_NONE;
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}
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else if (message->qspi_data_lines == 1)
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{
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Cmdhandler.DataMode = QSPI_DATA_1_LINE;
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}
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else if (message->qspi_data_lines == 2)
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{
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Cmdhandler.DataMode = QSPI_DATA_2_LINES;
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}
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else if (message->qspi_data_lines == 4)
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{
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Cmdhandler.DataMode = QSPI_DATA_4_LINES;
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}
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Cmdhandler.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
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Cmdhandler.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
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Cmdhandler.DdrMode = QSPI_DDR_MODE_DISABLE;
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Cmdhandler.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
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Cmdhandler.NbData = message->parent.length;
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HAL_QSPI_Command(&qspi_bus->QSPI_Handler, &Cmdhandler, 5000);
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}
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static rt_uint32_t qspixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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rt_size_t len = 0;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
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struct stm32_qspi_bus *qspi_bus = device->bus->parent.user_data;
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#ifdef BSP_QSPI_USING_SOFTCS
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struct stm32_hw_spi_cs *cs = device->parent.user_data;
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#endif
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const rt_uint8_t *sndb = message->send_buf;
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rt_uint8_t *rcvb = message->recv_buf;
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rt_int32_t length = message->length;
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#ifdef BSP_QSPI_USING_SOFTCS
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if (message->cs_take)
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{
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rt_pin_write(cs->pin, 0);
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}
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#endif
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/* send data */
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if (sndb)
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{
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qspi_send_cmd(qspi_bus, qspi_message);
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if (qspi_message->parent.length != 0)
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{
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if (HAL_QSPI_Transmit(&qspi_bus->QSPI_Handler, (rt_uint8_t *)sndb, 5000) == HAL_OK)
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{
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len = length;
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}
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else
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{
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LOG_E("QSPI send data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
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qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
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goto __exit;
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}
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}
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else
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{
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len = 1;
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}
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}
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else if (rcvb)/* recv data */
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{
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qspi_send_cmd(qspi_bus, qspi_message);
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#ifdef BSP_QSPI_USING_DMA
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if (HAL_QSPI_Receive_DMA(&qspi_bus->QSPI_Handler, rcvb) == HAL_OK)
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#else
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if (HAL_QSPI_Receive(&qspi_bus->QSPI_Handler, rcvb, 5000) == HAL_OK)
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#endif
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{
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len = length;
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#ifdef BSP_QSPI_USING_DMA
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while (qspi_bus->QSPI_Handler.RxXferCount != 0);
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#endif
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}
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else
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{
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LOG_E("QSPI recv data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
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qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
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goto __exit;
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}
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}
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__exit:
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#ifdef BSP_QSPI_USING_SOFTCS
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if (message->cs_release)
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{
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rt_pin_write(cs->pin, 1);
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}
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#endif
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return len;
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}
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static rt_err_t qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device;
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return stm32_qspi_init(qspi_device, &qspi_device->config);
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}
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static const struct rt_spi_ops stm32_qspi_ops =
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{
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.configure = qspi_configure,
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.xfer = qspixfer,
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};
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static int stm32_qspi_register_bus(struct stm32_qspi_bus *qspi_bus, const char *name)
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{
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RT_ASSERT(qspi_bus != RT_NULL);
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RT_ASSERT(name != RT_NULL);
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_qspi_bus1.parent.user_data = qspi_bus;
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return rt_qspi_bus_register(&_qspi_bus1, name, &stm32_qspi_ops);
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}
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/**
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* @brief This function attach device to QSPI bus.
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* @param device_name QSPI device name
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* @param pin QSPI cs pin number
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* @param data_line_width QSPI data lines width, such as 1, 2, 4
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* @param enter_qspi_mode Callback function that lets FLASH enter QSPI mode
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* @param exit_qspi_mode Callback function that lets FLASH exit QSPI mode
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* @retval 0 : success
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* -1 : failed
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*/
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rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
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{
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struct rt_qspi_device *qspi_device = RT_NULL;
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struct stm32_hw_spi_cs *cs_pin = RT_NULL;
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rt_err_t result = RT_EOK;
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RT_ASSERT(bus_name != RT_NULL);
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RT_ASSERT(device_name != RT_NULL);
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RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
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qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
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if (qspi_device == RT_NULL)
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{
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LOG_E("no memory, qspi bus attach device failed!");
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result = RT_ENOMEM;
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goto __exit;
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}
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cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
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if (qspi_device == RT_NULL)
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{
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LOG_E("no memory, qspi bus attach device failed!");
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result = RT_ENOMEM;
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goto __exit;
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}
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qspi_device->enter_qspi_mode = enter_qspi_mode;
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qspi_device->exit_qspi_mode = exit_qspi_mode;
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qspi_device->config.qspi_dl_width = data_line_width;
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cs_pin->Pin = pin;
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#ifdef BSP_QSPI_USING_SOFTCS
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rt_pin_mode(pin, PIN_MODE_OUTPUT);
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rt_pin_write(pin, 1);
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#endif
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result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, (void *)cs_pin);
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__exit:
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if (result != RT_EOK)
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{
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if (qspi_device)
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{
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rt_free(qspi_device);
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}
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if (cs_pin)
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{
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rt_free(cs_pin);
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}
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}
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return result;
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}
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#ifdef BSP_QSPI_USING_DMA
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void QSPI_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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HAL_QSPI_IRQHandler(&_stm32_qspi_bus.QSPI_Handler);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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void QSPI_DMA_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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HAL_DMA_IRQHandler(&_stm32_qspi_bus.hdma_quadspi);
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||
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/* leave interrupt */
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||
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rt_interrupt_leave();
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||
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}
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#endif /* BSP_QSPI_USING_DMA */
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||
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||
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static int rt_hw_qspi_bus_init(void)
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||
|
|
{
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return stm32_qspi_register_bus(&_stm32_qspi_bus, "qspi1");
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}
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INIT_BOARD_EXPORT(rt_hw_qspi_bus_init);
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||
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||
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#endif /* BSP_USING_QSPI */
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||
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#endif /* RT_USING_QSPI */
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