567 lines
14 KiB
C
567 lines
14 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-13 zylx first version
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*/
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#include <board.h>
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#include<rtthread.h>
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#include<rtdevice.h>
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#ifdef RT_USING_PWM
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#include "drv_config.h"
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//#define DRV_DEBUG
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#define LOG_TAG "drv.pwm"
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#include <drv_log.h>
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#define MAX_PERIOD 65535
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#define MIN_PERIOD 3
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#define MIN_PULSE 2
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extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
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enum
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{
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#ifdef BSP_USING_PWM1
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PWM1_INDEX,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_INDEX,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_INDEX,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM6
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PWM6_INDEX,
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#endif
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#ifdef BSP_USING_PWM7
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PWM7_INDEX,
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#endif
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#ifdef BSP_USING_PWM8
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PWM8_INDEX,
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#endif
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#ifdef BSP_USING_PWM9
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PWM9_INDEX,
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#endif
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#ifdef BSP_USING_PWM10
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PWM10_INDEX,
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#endif
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#ifdef BSP_USING_PWM11
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PWM11_INDEX,
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#endif
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#ifdef BSP_USING_PWM12
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PWM12_INDEX,
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#endif
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#ifdef BSP_USING_PWM13
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PWM13_INDEX,
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#endif
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#ifdef BSP_USING_PWM14
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PWM14_INDEX,
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#endif
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#ifdef BSP_USING_PWM15
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PWM15_INDEX,
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#endif
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#ifdef BSP_USING_PWM16
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PWM16_INDEX,
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#endif
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#ifdef BSP_USING_PWM17
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PWM17_INDEX,
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#endif
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};
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struct stm32_pwm
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{
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struct rt_device_pwm pwm_device;
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TIM_HandleTypeDef tim_handle;
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rt_uint8_t channel;
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char *name;
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};
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static struct stm32_pwm stm32_pwm_obj[] =
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{
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#ifdef BSP_USING_PWM1
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PWM1_CONFIG,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_CONFIG,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_CONFIG,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_CONFIG,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_CONFIG,
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#endif
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#ifdef BSP_USING_PWM6
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PWM6_CONFIG,
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#endif
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#ifdef BSP_USING_PWM7
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PWM7_CONFIG,
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#endif
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#ifdef BSP_USING_PWM8
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PWM8_CONFIG,
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#endif
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#ifdef BSP_USING_PWM9
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PWM9_CONFIG,
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#endif
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#ifdef BSP_USING_PWM10
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PWM10_CONFIG,
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#endif
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#ifdef BSP_USING_PWM11
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PWM11_CONFIG,
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#endif
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#ifdef BSP_USING_PWM12
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PWM12_CONFIG,
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#endif
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#ifdef BSP_USING_PWM13
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PWM13_CONFIG,
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#endif
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#ifdef BSP_USING_PWM14
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PWM14_CONFIG,
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#endif
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#ifdef BSP_USING_PWM15
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PWM15_CONFIG,
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#endif
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#ifdef BSP_USING_PWM16
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PWM16_CONFIG,
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#endif
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#ifdef BSP_USING_PWM17
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PWM17_CONFIG,
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#endif
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};
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops drv_ops =
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{
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drv_pwm_control
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};
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static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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/* Converts the channel number to the channel number of Hal library */
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rt_uint32_t channel = 0x04 * (configuration->channel - 1);
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if (!enable)
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{
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HAL_TIM_PWM_Stop(htim, channel);
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}
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else
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{
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HAL_TIM_PWM_Start(htim, channel);
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
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{
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/* Converts the channel number to the channel number of Hal library */
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rt_uint32_t channel = 0x04 * (configuration->channel - 1);
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rt_uint64_t tim_clock;
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#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
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#elif defined(SOC_SERIES_STM32L4)
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if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
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#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
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if (0)
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#endif
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{
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#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
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tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
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#endif
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}
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else
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{
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#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
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tim_clock = HAL_RCC_GetPCLK1Freq();
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#else
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tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
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#endif
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}
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if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
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{
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tim_clock = tim_clock / 2;
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}
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else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
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{
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tim_clock = tim_clock / 4;
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}
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/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
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tim_clock /= 1000000UL;
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configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
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configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t period, pulse;
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rt_uint64_t tim_clock, psc;
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/* Converts the channel number to the channel number of Hal library */
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rt_uint32_t channel = 0x04 * (configuration->channel - 1);
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#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
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#elif defined(SOC_SERIES_STM32L4)
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if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
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#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
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if (0)
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#endif
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{
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#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
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tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
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#endif
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}
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else
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{
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#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
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tim_clock = HAL_RCC_GetPCLK1Freq();
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#else
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tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
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#endif
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}
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/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
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tim_clock /= 1000000UL;
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period = (unsigned long long)configuration->period * tim_clock / 1000ULL ;
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psc = period / MAX_PERIOD + 1;
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period = period / psc;
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__HAL_TIM_SET_PRESCALER(htim, psc - 1);
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if (period < MIN_PERIOD)
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{
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period = MIN_PERIOD;
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}
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__HAL_TIM_SET_AUTORELOAD(htim, period - 1);
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pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL;
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if (pulse < MIN_PULSE)
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{
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pulse = MIN_PULSE;
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}
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else if (pulse > period)
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{
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pulse = period;
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}
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__HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
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__HAL_TIM_SET_COUNTER(htim, 0);
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/* Update frequency value */
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HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return drv_pwm_enable(htim, configuration, RT_TRUE);
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case PWM_CMD_DISABLE:
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return drv_pwm_enable(htim, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return drv_pwm_set(htim, configuration);
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case PWM_CMD_GET:
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return drv_pwm_get(htim, configuration);
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default:
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return RT_EINVAL;
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}
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}
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static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
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{
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rt_err_t result = RT_EOK;
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TIM_HandleTypeDef *tim = RT_NULL;
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TIM_OC_InitTypeDef oc_config = {0};
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TIM_MasterConfigTypeDef master_config = {0};
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TIM_ClockConfigTypeDef clock_config = {0};
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RT_ASSERT(device != RT_NULL);
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tim = (TIM_HandleTypeDef *)&device->tim_handle;
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/* configure the timer to pwm mode */
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tim->Init.Prescaler = 0;
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tim->Init.CounterMode = TIM_COUNTERMODE_UP;
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tim->Init.Period = 0;
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tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
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#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
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tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
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#endif
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if (HAL_TIM_PWM_Init(tim) != HAL_OK)
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{
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LOG_E("%s pwm init failed", device->name);
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result = -RT_ERROR;
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goto __exit;
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}
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clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
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if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
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{
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LOG_E("%s clock init failed", device->name);
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result = -RT_ERROR;
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goto __exit;
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}
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master_config.MasterOutputTrigger = TIM_TRGO_RESET;
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master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
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if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
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{
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LOG_E("%s master config failed", device->name);
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result = -RT_ERROR;
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goto __exit;
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}
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oc_config.OCMode = TIM_OCMODE_PWM1;
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oc_config.Pulse = 0;
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oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
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oc_config.OCFastMode = TIM_OCFAST_DISABLE;
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oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
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oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
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/* config pwm channel */
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if (device->channel & 0x01)
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{
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if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
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{
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LOG_E("%s channel1 config failed", device->name);
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result = -RT_ERROR;
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goto __exit;
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}
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}
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if (device->channel & 0x02)
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{
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|
|
if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
|
||
|
|
{
|
||
|
|
LOG_E("%s channel2 config failed", device->name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
goto __exit;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (device->channel & 0x04)
|
||
|
|
{
|
||
|
|
if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
|
||
|
|
{
|
||
|
|
LOG_E("%s channel3 config failed", device->name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
goto __exit;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (device->channel & 0x08)
|
||
|
|
{
|
||
|
|
if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
|
||
|
|
{
|
||
|
|
LOG_E("%s channel4 config failed", device->name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
goto __exit;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* pwm pin configuration */
|
||
|
|
HAL_TIM_MspPostInit(tim);
|
||
|
|
|
||
|
|
/* enable update request source */
|
||
|
|
__HAL_TIM_URS_ENABLE(tim);
|
||
|
|
|
||
|
|
__exit:
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void pwm_get_channel(void)
|
||
|
|
{
|
||
|
|
#ifdef BSP_USING_PWM1_CH1
|
||
|
|
stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM1_CH2
|
||
|
|
stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM1_CH3
|
||
|
|
stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM1_CH4
|
||
|
|
stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM2_CH1
|
||
|
|
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM2_CH2
|
||
|
|
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM2_CH3
|
||
|
|
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM2_CH4
|
||
|
|
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM3_CH1
|
||
|
|
stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM3_CH2
|
||
|
|
stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM3_CH3
|
||
|
|
stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM3_CH4
|
||
|
|
stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM4_CH1
|
||
|
|
stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM4_CH2
|
||
|
|
stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM4_CH3
|
||
|
|
stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM4_CH4
|
||
|
|
stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM5_CH1
|
||
|
|
stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM5_CH2
|
||
|
|
stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM5_CH3
|
||
|
|
stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM5_CH4
|
||
|
|
stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM6_CH1
|
||
|
|
stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM6_CH2
|
||
|
|
stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM6_CH3
|
||
|
|
stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM6_CH4
|
||
|
|
stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM7_CH1
|
||
|
|
stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM7_CH2
|
||
|
|
stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM7_CH3
|
||
|
|
stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM7_CH4
|
||
|
|
stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM8_CH1
|
||
|
|
stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM8_CH2
|
||
|
|
stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM8_CH3
|
||
|
|
stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM8_CH4
|
||
|
|
stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM9_CH1
|
||
|
|
stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM9_CH2
|
||
|
|
stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM9_CH3
|
||
|
|
stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM9_CH4
|
||
|
|
stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM12_CH1
|
||
|
|
stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM12_CH2
|
||
|
|
stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
static int stm32_pwm_init(void)
|
||
|
|
{
|
||
|
|
int i = 0;
|
||
|
|
int result = RT_EOK;
|
||
|
|
|
||
|
|
pwm_get_channel();
|
||
|
|
|
||
|
|
for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
|
||
|
|
{
|
||
|
|
/* pwm init */
|
||
|
|
if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_E("%s init failed", stm32_pwm_obj[i].name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
goto __exit;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_D("%s init success", stm32_pwm_obj[i].name);
|
||
|
|
|
||
|
|
/* register pwm device */
|
||
|
|
if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_D("%s register success", stm32_pwm_obj[i].name);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_E("%s register failed", stm32_pwm_obj[i].name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
__exit:
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
INIT_DEVICE_EXPORT(stm32_pwm_init);
|
||
|
|
#endif /* RT_USING_PWM */
|