97 lines
3.3 KiB
C
97 lines
3.3 KiB
C
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-10-26 ChenYong first version
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* 2020-01-08 xiangxistu add HSI configuration
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*/
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#include <board.h>
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#include <rtthread.h>
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#include <stm32f1xx.h>
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#include "drv_common.h"
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#define DBG_TAG "board"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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void system_clock_config(int target_freq_Mhz)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
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#if defined(STM32F100xB) || defined(STM32F100xE)
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
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#endif
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#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG)
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
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#endif
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#if defined(STM32F102x6) || defined(STM32F102xB)
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
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#endif
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#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
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#endif
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#if defined(STM32F105xC) || defined(STM32F107xC)
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
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#endif
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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#if defined(STM32F100xB) || defined(STM32F100xE)
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
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#endif
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#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG)
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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#endif
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#if defined(STM32F102x6) || defined(STM32F102xB)
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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#endif
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#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
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#endif
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#if defined(STM32F105xC) || defined(STM32F107xC)
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
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#endif
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{
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Error_Handler();
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}
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}
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int clock_information(void)
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{
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LOG_D("System Clock information");
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LOG_D("SYSCLK_Frequency = %d", HAL_RCC_GetSysClockFreq());
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LOG_D("HCLK_Frequency = %d", HAL_RCC_GetHCLKFreq());
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LOG_D("PCLK1_Frequency = %d", HAL_RCC_GetPCLK1Freq());
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LOG_D("PCLK2_Frequency = %d", HAL_RCC_GetPCLK2Freq());
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return RT_EOK;
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}
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INIT_BOARD_EXPORT(clock_information);
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void clk_init(char *clk_source, int source_freq, int target_freq)
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{
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system_clock_config(target_freq);
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}
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