303 lines
12 KiB
C
303 lines
12 KiB
C
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/**************************************************************************************************
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Filename: hal_dma.h
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Revised: $Date: 2011-05-31 11:57:28 -0700 (Tue, 31 May 2011) $
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Revision: $Revision: 26163 $
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Description: This file contains the interface to the DMA Service.
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Copyright 2007-2011 Texas Instruments Incorporated. All rights reserved.
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IMPORTANT: Your use of this Software is limited to those specific rights
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granted under the terms of a software license agreement between the user
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who downloaded the software, his/her employer (which must be your employer)
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and Texas Instruments Incorporated (the "License"). You may not use this
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Software unless you agree to abide by the terms of the License. The License
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limits your use, and you acknowledge, that the Software may not be modified,
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copied or distributed unless embedded on a Texas Instruments microcontroller
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or used solely and exclusively in conjunction with a Texas Instruments radio
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frequency transceiver, which is integrated into your product. Other than for
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the foregoing purpose, you may not use, reproduce, copy, prepare derivative
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works of, modify, distribute, perform, display or sell this Software and/or
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its documentation for any purpose.
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YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE
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PROVIDED <EFBFBD>AS IS<EFBFBD> WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
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INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE,
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NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL
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TEXAS INSTRUMENTS OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER CONTRACT,
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NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER
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LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES
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INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE
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OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT
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OF SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES
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(INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
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Should you have any questions regarding your right to use this Software,
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contact Texas Instruments Incorporated at www.TI.com.
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**************************************************************************************************/
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#ifndef HAL_DMA_H
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#define HAL_DMA_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*********************************************************************
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* INCLUDES
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*/
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#include "hal_board.h"
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#include "hal_types.h"
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#if ((defined HAL_DMA) && (HAL_DMA == TRUE))
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/*********************************************************************
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* MACROS
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*/
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#define HAL_DMA_SET_ADDR_DESC0( a ) \
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st( \
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DMA0CFGH = (uint8)( (uint16)(a) >> 8 ); \
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DMA0CFGL = (uint8)( (uint16)(a) & 0xFF ); \
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)
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#define HAL_DMA_SET_ADDR_DESC1234( a ) \
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st( \
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DMA1CFGH = (uint8)( (uint16)(a) >> 8 ); \
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DMA1CFGL = (uint8)( (uint16)(a) & 0xFF ); \
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)
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#define HAL_DMA_GET_DESC0() &dmaCh0
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#define HAL_DMA_GET_DESC1234( a ) (dmaCh1234+((a)-1))
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#define HAL_DMA_ARM_CH( ch ) DMAARM = (0x01 << (ch))
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#define HAL_DMA_CH_ARMED( ch ) (DMAARM & (0x01 << (ch)))
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#define HAL_DMA_ABORT_CH( ch ) DMAARM = (0x80 | (0x01 << (ch)))
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#define HAL_DMA_MAN_TRIGGER( ch ) DMAREQ = (0x01 << (ch))
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#define HAL_DMA_START_CH( ch ) HAL_DMA_MAN_TRIGGER( (ch) )
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#define HAL_DMA_CLEAR_IRQ( ch ) DMAIRQ = ((0x01 << (ch)) ^ 0xFF)
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#define HAL_DMA_CHECK_IRQ( ch ) (DMAIRQ & (0x01 << (ch)))
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// Macro for quickly setting the source address of a DMA structure.
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#define HAL_DMA_SET_SOURCE( pDesc, src ) \
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st( \
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pDesc->srcAddrH = (uint8)( (uint16)(src) >> 8 ); \
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pDesc->srcAddrL = (uint8)( (uint16)(src) & 0xFF ); \
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)
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// Macro for quickly setting the destination address of a DMA structure.
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#define HAL_DMA_SET_DEST( pDesc, dst ) \
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st( \
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pDesc->dstAddrH = (uint8)( (uint16)(dst) >> 8 ); \
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pDesc->dstAddrL = (uint8)( (uint16)(dst) & 0xFF ); \
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)
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// Macro for quickly setting the number of bytes to be transferred by the DMA,
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// max length is 0x1FFF.
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#define HAL_DMA_SET_LEN( pDesc, len ) \
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st( \
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pDesc->xferLenL = (uint8)( (uint16)(len) & 0xFF); \
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pDesc->xferLenV &= ~HAL_DMA_LEN_H; \
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pDesc->xferLenV |= (uint8)((uint16)(len) >> 8); \
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)
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#define HAL_DMA_GET_LEN( pDesc ) \
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(((uint16)(pDesc->xferLenV & HAL_DMA_LEN_H) << 8) | pDesc->xferLenL)
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#define HAL_DMA_SET_VLEN( pDesc, vMode ) \
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st( \
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pDesc->xferLenV &= ~HAL_DMA_LEN_V; \
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pDesc->xferLenV |= (vMode << 5); \
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)
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#define HAL_DMA_SET_WORD_SIZE( pDesc, xSz ) \
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st( \
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pDesc->ctrlA &= ~HAL_DMA_WORD_SIZE; \
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pDesc->ctrlA |= (xSz << 7); \
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)
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#define HAL_DMA_SET_TRIG_MODE( pDesc, tMode ) \
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st( \
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pDesc->ctrlA &= ~HAL_DMA_TRIG_MODE; \
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pDesc->ctrlA |= (tMode << 5); \
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)
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#define HAL_DMA_GET_TRIG_MODE( pDesc ) ((pDesc->ctrlA >> 5) & 0x3)
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#define HAL_DMA_SET_TRIG_SRC( pDesc, tSrc ) \
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st( \
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pDesc->ctrlA &= ~HAL_DMA_TRIG_SRC; \
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pDesc->ctrlA |= tSrc; \
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)
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#define HAL_DMA_SET_SRC_INC( pDesc, srcInc ) \
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st( \
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pDesc->ctrlB &= ~HAL_DMA_SRC_INC; \
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pDesc->ctrlB |= (srcInc << 6); \
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)
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#define HAL_DMA_SET_DST_INC( pDesc, dstInc ) \
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st( \
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pDesc->ctrlB &= ~HAL_DMA_DST_INC; \
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pDesc->ctrlB |= (dstInc << 4); \
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)
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#define HAL_DMA_SET_IRQ( pDesc, enable ) \
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st( \
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pDesc->ctrlB &= ~HAL_DMA_IRQ_MASK; \
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pDesc->ctrlB |= (enable << 3); \
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)
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#define HAL_DMA_SET_M8( pDesc, m8 ) \
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st( \
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pDesc->ctrlB &= ~HAL_DMA_M8; \
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pDesc->ctrlB |= (m8 << 2); \
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)
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#define HAL_DMA_SET_PRIORITY( pDesc, pri ) \
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st( \
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pDesc->ctrlB &= ~HAL_DMA_PRIORITY; \
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pDesc->ctrlB |= pri; \
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)
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/*********************************************************************
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* CONSTANTS
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*/
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// Use LEN for transfer count
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#define HAL_DMA_VLEN_USE_LEN 0x00
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// Transfer the first byte + the number of bytes indicated by the first byte
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#define HAL_DMA_VLEN_1_P_VALOFFIRST 0x01
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// Transfer the number of bytes indicated by the first byte (starting with the first byte)
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#define HAL_DMA_VLEN_VALOFFIRST 0x02
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// Transfer the first byte + the number of bytes indicated by the first byte + 1 more byte
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#define HAL_DMA_VLEN_1_P_VALOFFIRST_P_1 0x03
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// Transfer the first byte + the number of bytes indicated by the first byte + 2 more bytes
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#define HAL_DMA_VLEN_1_P_VALOFFIRST_P_2 0x04
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#define HAL_DMA_WORDSIZE_BYTE 0x00 /* Transfer a byte at a time. */
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#define HAL_DMA_WORDSIZE_WORD 0x01 /* Transfer a 16-bit word at a time. */
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#define HAL_DMA_TMODE_SINGLE 0x00 /* Transfer a single byte/word after each DMA trigger. */
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#define HAL_DMA_TMODE_BLOCK 0x01 /* Transfer block of data (length len) after each DMA trigger. */
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#define HAL_DMA_TMODE_SINGLE_REPEATED 0x02 /* Transfer single byte/word (after len transfers, rearm DMA). */
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#define HAL_DMA_TMODE_BLOCK_REPEATED 0x03 /* Transfer block of data (after len transfers, rearm DMA). */
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#define HAL_DMA_TRIG_NONE 0 /* No trigger, setting DMAREQ.DMAREQx bit starts transfer. */
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#define HAL_DMA_TRIG_PREV 1 /* DMA channel is triggered by completion of previous channel. */
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#define HAL_DMA_TRIG_T1_CH0 2 /* Timer 1, compare, channel 0. */
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#define HAL_DMA_TRIG_T1_CH1 3 /* Timer 1, compare, channel 1. */
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#define HAL_DMA_TRIG_T1_CH2 4 /* Timer 1, compare, channel 2. */
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#define HAL_DMA_TRIG_T2_COMP 5 /* Timer 2, compare. */
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#define HAL_DMA_TRIG_T2_OVFL 6 /* Timer 2, overflow. */
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#define HAL_DMA_TRIG_T3_CH0 7 /* Timer 3, compare, channel 0. */
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#define HAL_DMA_TRIG_T3_CH1 8 /* Timer 3, compare, channel 1. */
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#define HAL_DMA_TRIG_T4_CH0 9 /* Timer 4, compare, channel 0. */
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#define HAL_DMA_TRIG_T4_CH1 10 /* Timer 4, compare, channel 1. */
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#define HAL_DMA_TRIG_ST 11 /* Sleep Timer compare. */
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#define HAL_DMA_TRIG_IOC_0 12 /* Port 0 I/O pin input transition. */
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#define HAL_DMA_TRIG_IOC_1 13 /* Port 1 I/O pin input transition. */
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#define HAL_DMA_TRIG_URX0 14 /* USART0 RX complete. */
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#define HAL_DMA_TRIG_UTX0 15 /* USART0 TX complete. */
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#define HAL_DMA_TRIG_URX1 16 /* USART1 RX complete. */
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#define HAL_DMA_TRIG_UTX1 17 /* USART1 TX complete. */
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#define HAL_DMA_TRIG_FLASH 18 /* Flash data write complete. */
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#define HAL_DMA_TRIG_RADIO 19 /* RF packet byte received/transmit. */
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#define HAL_DMA_TRIG_ADC_CHALL 20 /* ADC end of a conversion in a sequence, sample ready. */
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#define HAL_DMA_TRIG_ADC_CH0 21 /* ADC end of conversion channel 0 in sequence, sample ready. */
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#define HAL_DMA_TRIG_ADC_CH1 22 /* ADC end of conversion channel 1 in sequence, sample ready. */
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#define HAL_DMA_TRIG_ADC_CH2 23 /* ADC end of conversion channel 2 in sequence, sample ready. */
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#define HAL_DMA_TRIG_ADC_CH3 24 /* ADC end of conversion channel 3 in sequence, sample ready. */
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#define HAL_DMA_TRIG_ADC_CH4 25 /* ADC end of conversion channel 4 in sequence, sample ready. */
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#define HAL_DMA_TRIG_ADC_CH5 26 /* ADC end of conversion channel 5 in sequence, sample ready. */
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#define HAL_DMA_TRIG_ADC_CH6 27 /* ADC end of conversion channel 6 in sequence, sample ready. */
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#define HAL_DMA_TRIG_ADC_CH7 28 /* ADC end of conversion channel 7 in sequence, sample ready. */
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#define HAL_DMA_TRIG_ENC_DW 29 /* AES encryption processor requests download input data. */
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#define HAL_DMA_TRIG_ENC_UP 30 /* AES encryption processor requests upload output data. */
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#define HAL_DMA_SRCINC_0 0x00 /* Increment source pointer by 0 bytes/words after each transfer. */
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#define HAL_DMA_SRCINC_1 0x01 /* Increment source pointer by 1 bytes/words after each transfer. */
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#define HAL_DMA_SRCINC_2 0x02 /* Increment source pointer by 2 bytes/words after each transfer. */
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#define HAL_DMA_SRCINC_M1 0x03 /* Decrement source pointer by 1 bytes/words after each transfer. */
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#define HAL_DMA_DSTINC_0 0x00 /* Increment destination pointer by 0 bytes/words after each transfer. */
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#define HAL_DMA_DSTINC_1 0x01 /* Increment destination pointer by 1 bytes/words after each transfer. */
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#define HAL_DMA_DSTINC_2 0x02 /* Increment destination pointer by 2 bytes/words after each transfer. */
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#define HAL_DMA_DSTINC_M1 0x03 /* Decrement destination pointer by 1 bytes/words after each transfer. */
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#define HAL_DMA_IRQMASK_DISABLE 0x00 /* Disable interrupt generation. */
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#define HAL_DMA_IRQMASK_ENABLE 0x01 /* Enable interrupt generation upon DMA channel done. */
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#define HAL_DMA_M8_USE_8_BITS 0x00 /* Use all 8 bits for transfer count. */
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#define HAL_DMA_M8_USE_7_BITS 0x01 /* Use 7 LSB for transfer count. */
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#define HAL_DMA_PRI_LOW 0x00 /* Low, CPU has priority. */
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#define HAL_DMA_PRI_GUARANTEED 0x01 /* Guaranteed, DMA at least every second try. */
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#define HAL_DMA_PRI_HIGH 0x02 /* High, DMA has priority. */
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#define HAL_DMA_PRI_ABSOLUTE 0x03 /* Highest, DMA has priority. Reserved for DMA port access.. */
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#define HAL_DMA_MAX_ARM_CLOCKS 45 // Maximum number of clocks required if arming all 5 at once.
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/*********************************************************************
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* TYPEDEFS
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*/
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// Bit fields of the 'lenModeH'
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#define HAL_DMA_LEN_V 0xE0
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#define HAL_DMA_LEN_H 0x1F
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// Bit fields of the 'ctrlA'
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#define HAL_DMA_WORD_SIZE 0x80
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#define HAL_DMA_TRIG_MODE 0x60
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#define HAL_DMA_TRIG_SRC 0x1F
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// Bit fields of the 'ctrlB'
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#define HAL_DMA_SRC_INC 0xC0
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#define HAL_DMA_DST_INC 0x30
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#define HAL_DMA_IRQ_MASK 0x08
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#define HAL_DMA_M8 0x04
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#define HAL_DMA_PRIORITY 0x03
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typedef struct {
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uint8 srcAddrH;
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uint8 srcAddrL;
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uint8 dstAddrH;
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uint8 dstAddrL;
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uint8 xferLenV;
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uint8 xferLenL;
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uint8 ctrlA;
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uint8 ctrlB;
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} halDMADesc_t;
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/*********************************************************************
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* GLOBAL VARIABLES
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*/
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extern halDMADesc_t dmaCh0;
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extern halDMADesc_t dmaCh1234[4];
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/*********************************************************************
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* FUNCTIONS - API
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*/
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void HalDmaInit( void );
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#endif // #if (defined HAL_DMA) && (HAL_DMA == TRUE)
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#ifdef __cplusplus
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}
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#endif
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#endif // #ifndef HAL_DMA_H
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/******************************************************************************
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******************************************************************************/
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